From c3ff1addde6f92211934beed50261eccd8b8028b Mon Sep 17 00:00:00 2001
From: Pierce Chou <chou.pierce@inventec.corp-partner.google.com>
Date: Tue, 16 Dec 2025 13:13:32 +0800
Subject: [PATCH] mb/google/ocelot/var/ocicat: Add WIFI SAR table

- Add WIFI SAR table for intel WIFI SAR table
- Follow new UFSC definitions to rename WIFI config

BUG=b:469226622
TEST=Build and flash to DUT, check that SAR table is
loaded by cbmem -1 | grep sar

Change-Id: Iba3c4588c969a74dd83d176124addfa2d115edbd
Signed-off-by: Pierce Chou <chou.pierce@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../ocelot/variants/ocicat/overridetree.cb       | 16 ++++++++--------
 .../google/ocelot/variants/ocicat/variant.c      |  5 +++++
 2 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb b/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
index e1f32ada9b..03f782fad3 100644
--- a/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
@@ -1,9 +1,4 @@
 fw_config
-	field WIFI 2 4
-		option WIFI_NONE			0
-		option WIFI_CNVI_7			1
-		option WIFI_PCIE_7			2
-	end
 	field STORAGE_TYPE 12 14
 		option STORAGE_TYPE_UNKNOWN		0
 		option STORAGE_TYPE_NVME_GEN4		1
@@ -14,6 +9,11 @@ fw_config
 		option TOUCH_ELAN_TOP	1
 		option TOUCH_ELAN_DBTS	2
 	end
+	field WIFI_INTERFACE 26 27
+		option WIFI_INTERFACE_UNKNOWN		0
+		option WIFI_INTERFACE_CNVI_7		1
+		option WIFI_INTERFACE_PCIE_7		2
+	end
 end
 
 chip soc/intel/pantherlake
@@ -328,7 +328,7 @@ chip soc/intel/pantherlake
 						register "type" = "UPC_TYPE_INTERNAL"
 						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B09)"
 						device ref usb2_port8 on
-							probe WIFI WIFI_PCIE_7
+                                                       probe WIFI_INTERFACE WIFI_INTERFACE_PCIE_7
 	                                	end
 
 					end
@@ -365,7 +365,7 @@ chip soc/intel/pantherlake
 		end # Gen4 M.2 SSD
 
 		device ref pcie_rp5 on
-			probe WIFI WIFI_PCIE_7
+			probe WIFI_INTERFACE WIFI_INTERFACE_PCIE_7
 			register "pcie_rp[PCIE_RP(5)]" = "{
 			.clk_src = 0,
 			.clk_req = 0,
@@ -384,7 +384,7 @@ chip soc/intel/pantherlake
 		end # CNVi
 
 		device ref cnvi_bluetooth on
-			probe WIFI WIFI_CNVI_7
+			probe WIFI_INTERFACE WIFI_INTERFACE_CNVI_7
 			chip soc/intel/common/block/cnvi
 				register "wake" = "GPE0_PME_B0"
 				device generic 0 on end
diff --git a/src/mainboard/google/ocelot/variants/ocicat/variant.c b/src/mainboard/google/ocelot/variants/ocicat/variant.c
index a7154dada0..733cf6bf3b 100644
--- a/src/mainboard/google/ocelot/variants/ocicat/variant.c
+++ b/src/mainboard/google/ocelot/variants/ocicat/variant.c
@@ -10,6 +10,11 @@
 #include <soc/gpio_soc_defs.h>
 #include <drivers/intel/touch/chip.h>
 
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_INTERFACE));
+}
+
 void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
 {
 	FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;