ACPI: Replace smm_setup_structures()

Except for whitespace and varying casts the codes were
the same when implemented.

Platforms that did not implement this are tagged with
ACPI_NO_SMI_GNVS.

Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/amd/picasso/Kconfig

@@ -56,6 +56,7 @@ config CPU_SPECIFIC_OPTIONS
 	select UDK_2017_BINDING
 	select HAVE_CF9_RESET
 	select SUPPORT_CPU_UCODE_IN_CBFS
+	select ACPI_NO_SMI_GNVS
 
 config MEMLAYOUT_LD_FILE
 	string

src/soc/amd/picasso/smi.c

@@ -11,11 +11,6 @@
 #include <soc/southbridge.h>
 #include <soc/smi.h>
 
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
-{
-	printk(BIOS_DEBUG, "%s STUB!!!\n", __func__);
-}
-
 /** Set the EOS bit and enable SMI generation from southbridge */
 void global_smi_enable(void)
 {

src/soc/amd/stoneyridge/Kconfig

@@ -46,6 +46,7 @@ config CPU_SPECIFIC_OPTIONS
 	select HAVE_SMI_HANDLER
 	select SSE2
 	select RTC
+	select ACPI_NO_SMI_GNVS
 
 config AMD_APU_STONEYRIDGE
 	bool

src/soc/amd/stoneyridge/smi.c

@@ -10,11 +10,6 @@
 #include <soc/southbridge.h>
 #include <soc/smi.h>
 
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
-{
-	printk(BIOS_DEBUG, "%s STUB!!!\n", __func__);
-}
-
 /** Set the EOS bit and enable SMI generation from southbridge */
 void global_smi_enable(void)
 {

src/soc/intel/baytrail/smm.c

@@ -97,22 +97,3 @@ void global_smi_enable(void)
 {
 	smm_southbridge_enable(PWRBTN_EN | GBL_EN);
 }
-
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
-{
-	/*
-	 * Issue SMI to set the gnvs pointer in SMM.
-	 * tcg and smi1 are unused.
-	 *
-	 * EAX = APM_CNT_GNVS_UPDATE
-	 * EBX = gnvs pointer
-	 * EDX = APM_CNT
-	 */
-	asm volatile (
-		"outb %%al, %%dx\n\t"
-		: /* ignore result */
-		: "a" (APM_CNT_GNVS_UPDATE),
-		  "b" ((uint32_t)gnvs),
-		  "d" (APM_CNT)
-	);
-}

src/soc/intel/baytrail/southcluster.c

@@ -494,7 +494,7 @@ static void southcluster_inject_dsdt(const struct device *device)
 	if (gnvs) {
 		acpi_create_gnvs(gnvs);
 		/* And tell SMI about it */
-		smm_setup_structures(gnvs, NULL, NULL);
+		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to DSDT.  */
 		acpigen_write_scope("\\");

src/soc/intel/braswell/acpi.c

@@ -512,7 +512,7 @@ void southcluster_inject_dsdt(const struct device *device)
 			gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN;
 
 		/* And tell SMI about it */
-		smm_setup_structures(gnvs, NULL, NULL);
+		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to DSDT */
 		acpigen_write_scope("\\");

src/soc/intel/braswell/smm.c

@@ -99,22 +99,3 @@ void global_smi_enable(void)
 {
 	smm_southbridge_enable(PWRBTN_EN | GBL_EN);
 }
-
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
-{
-	/*
-	 * Issue SMI to set the gnvs pointer in SMM.
-	 * tcg and smi1 are unused.
-	 *
-	 * EAX = APM_CNT_GNVS_UPDATE
-	 * EBX = gnvs pointer
-	 * EDX = APM_CNT
-	 */
-	asm volatile (
-		"outb %%al, %%dx\n\t"
-		: /* ignore result */
-		: "a" (APM_CNT_GNVS_UPDATE),
-		  "b" ((uint32_t)gnvs),
-		  "d" (APM_CNT)
-	);
-}

src/soc/intel/broadwell/lpc.c

@@ -584,7 +584,7 @@ static void southcluster_inject_dsdt(const struct device *device)
 	if (gnvs) {
 		acpi_create_gnvs(gnvs);
 		/* And tell SMI about it */
-		smm_setup_structures(gnvs, NULL, NULL);
+		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to DSDT.  */
 		acpigen_write_scope("\\");

src/soc/intel/broadwell/smi.c

@@ -86,22 +86,3 @@ static void __unused southbridge_clear_smi_status(void)
 	/* Set EOS bit so other SMIs can occur. */
 	enable_smi(EOS);
 }
-
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
-{
-	/*
-	 * Issue SMI to set the gnvs pointer in SMM.
-	 * tcg and smi1 are unused.
-	 *
-	 * EAX = APM_CNT_GNVS_UPDATE
-	 * EBX = gnvs pointer
-	 * EDX = APM_CNT
-	 */
-	asm volatile (
-		"outb %%al, %%dx\n\t"
-		: /* ignore result */
-		: "a" (APM_CNT_GNVS_UPDATE),
-		  "b" ((u32)gnvs),
-		  "d" (APM_CNT)
-	);
-}

src/soc/intel/common/block/acpi/acpi.c

@@ -240,7 +240,7 @@ void southbridge_inject_dsdt(const struct device *device)
 	if (gnvs) {
 		acpi_create_gnvs(gnvs);
 		/* And tell SMI about it */
-		smm_setup_structures(gnvs, NULL, NULL);
+		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to DSDT.  */
 		acpigen_write_scope("\\");

src/soc/intel/common/block/smm/smm.c

@@ -70,22 +70,3 @@ void global_smi_enable_no_pwrbtn(void)
 {
 	smm_southbridge_enable(GBL_EN);
 }
-
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
-{
-	/*
-	 * Issue SMI to set the gnvs pointer in SMM.
-	 * tcg and smi1 are unused.
-	 *
-	 * EAX = APM_CNT_GNVS_UPDATE
-	 * EBX = gnvs pointer
-	 * EDX = APM_CNT
-	 */
-	asm volatile (
-		"outb %%al, %%dx\n\t"
-		: /* ignore result */
-		: "a" (APM_CNT_GNVS_UPDATE),
-		  "b" ((u32)gnvs),
-		  "d" (APM_CNT)
-	);
-}

src/soc/intel/denverton_ns/acpi.c

@@ -292,7 +292,7 @@ void southcluster_inject_dsdt(const struct device *device)
 	if (gnvs) {
 		acpi_create_gnvs(gnvs);
 		/* And tell SMI about it */
-		smm_setup_structures(gnvs, NULL, NULL);
+		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to DSDT.  */
 		acpigen_write_scope("\\");

src/soc/intel/denverton_ns/smm.c

@@ -56,19 +56,3 @@ void global_smi_enable(void)
 {
 	smm_southbridge_enable(PWRBTN_EN | GBL_EN);
 }
-
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
-{
-	/*
-	 * Issue SMI to set the gnvs pointer in SMM.
-	 * tcg and smi1 are unused.
-	 *
-	 * EAX = APM_CNT_GNVS_UPDATE
-	 * EBX = gnvs pointer
-	 * EDX = APM_CNT
-	 */
-	asm volatile("outb %%al, %%dx\n\t"
-		     : /* ignore result */
-		     : "a"(APM_CNT_GNVS_UPDATE), "b"((uint32_t)gnvs),
-		       "d"(APM_CNT));
-}

src/soc/intel/skylake/acpi.c

@@ -655,7 +655,7 @@ void southbridge_inject_dsdt(const struct device *device)
 	if (gnvs) {
 		acpi_create_gnvs(gnvs);
 		/* And tell SMI about it */
-		smm_setup_structures(gnvs, NULL, NULL);
+		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to DSDT.  */
 		acpigen_write_scope("\\");

src/soc/intel/xeon_sp/Kconfig

@@ -38,6 +38,7 @@ config	CPU_SPECIFIC_OPTIONS
 	select POSTCAR_STAGE
 	select IOAPIC
 	select PARALLEL_MP
+	select ACPI_NO_SMI_GNVS
 	select SMP
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select SOC_INTEL_COMMON_BLOCK

src/soc/intel/xeon_sp/cpx/acpi.c

@@ -120,7 +120,7 @@ void southbridge_inject_dsdt(const struct device *device)
 	if (gnvs) {
 		acpi_create_gnvs(gnvs);
 		/* TODO: tell SMI about it, if HAVE_SMI_HANDLER */
-		// smm_setup_structures(gnvs, NULL, NULL);
+		// apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to DSDT.  */
 		printk(BIOS_SPEW, "%s injecting NVSA with 0x%x\n", __FILE__, (uint32_t)gnvs);

src/soc/intel/xeon_sp/skx/acpi.c

@@ -968,7 +968,7 @@ void southbridge_inject_dsdt(const struct device *device)
 	if (gnvs) {
 		acpi_create_gnvs(gnvs);
 		/* TODO: tell SMI about it, if HAVE_SMI_HANDLER */
-		// smm_setup_structures(gnvs, NULL, NULL);
+		// apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to DSDT.  */
 		printk(BIOS_SPEW, "%s injecting NVSA with 0x%x\n", __FILE__, (uint32_t)gnvs);