soc/qualcomm/x1p42100: Update memlayout for BL31 region and realign TA region

TF-A feature additions have increased BL31 memory requirements. Expand
BL31 reservation from 600KB to 800KB and adjust the TA region start
address to prevent overlap. The TA region change requires FDT memory
reservation updates, which are handled in Depthcharge.This update
ensures proper memory alignment for secure firmware execution.

TEST=Created image.serial.bin and verified successful boot on X1P42100.
Basic device boot functionality with the updated memory reservation has
been validated.

Change-Id: Ia0145c9e8d5925de4a7fee3399efc76059944c10
Signed-off-by: Kirubakaran E <kirue@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Kirubakaran E 2025-12-03 21:21:42 -08:00 committed by Matt DeVillier
commit c3afc13a0a

View file

@ -30,9 +30,9 @@
* | dram_display | | |
* 0xE4800000 +----------------------------------------------------------+ | |
* | ... Usable memory ... | | |
* 0xD9600000 +----------------------------------------------------------+ | |
* 0xD9632000 +----------------------------------------------------------+ | |
* | dram_ta | | |
* 0xD8600000 +----------------------------------------------------------+ | |
* 0xD8632000 +----------------------------------------------------------+ | |
* | BL31 (ARM Trusted Firmware) | | |
* 0xD856A000 +----------------------------------------------------------+ | |
* | dram_tz (TrustZone) | | |
@ -242,8 +242,8 @@ SECTIONS
POSTRAM_CBFS_CACHE(0x9F800000, 16M)
RAMSTAGE(0xA0800000, 16M)
REGION(dram_tz, 0xD8000000, 0x56A000, 4K)
BL31(0xD856A000, 600K)
REGION(dram_ta, 0xD8600000, 0x1000000, 4K)
BL31(0xD856A000, 800K)
REGION(dram_ta, 0xD8632000, 0x1000000, 4K)
REGION(dram_display, 0xE4800000, 0x21C0000, 4K)
REGION(dram_llcc_lpi, 0xFF800000, 0x600000, 4K)
REGION(dram_smem, 0xFFE00000, 0x200000, 4K)