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exynos: Set up caching in the bootblock.

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This improves firmware boot time substantially. Because cbmem isn't available
yet, we need to allocate some space in sram for the ttb. Doing cache
initialization in the bootblock means we can implement this once per CPU
instead of once per mainboard.

BUG=chrome-os-partner:19420
TEST=Built and booted on pit. Built and booted on snow.
BRANCH=None

Change-Id: Iad339de24df8ec2e23f91fe7bf57744e4cc766c5
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/65938
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
Gabe Black 2013-08-13 21:05:43 -07:00 • committed by ChromeBot
commit c32b9b32ad
7 changed files with 46 additions and 40 deletions
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9
src/cpu/samsung/exynos5250/Kconfig
View file

@ -85,6 +85,15 @@ config CBFS_CACHE_SIZE
hex "size of CBFS cache data"
default 0x00018000
# TTB needs to be aligned to 16KB.
config TTB_BUFFER
hex "memory address of the TTB buffer"
default 0x02058000
config TTB_SIZE
hex "size of the TTB buffer"
default 0x4000
config SYS_SDRAM_BASE
hex
default 0x40000000

9
src/cpu/samsung/exynos5420/Kconfig
View file

@ -46,6 +46,7 @@ config CBFS_ROM_OFFSET
# 0x0202_4400: variable length bootblock checksum header.
# 0x0202_4410: bootblock, assume up to 32KB in size
# 0x0203_0000: romstage, assume up to 128KB in size.
# 0x0205_8000: TTB buffer.
# 0x0205_c000: cache for CBFS data.
# 0x0206_f000: stack bottom
# 0x0207_3000: stack pointer
@ -110,6 +111,14 @@ config CBFS_CACHE_SIZE
hex "size of CBFS cache data"
default 0x00013000
config TTB_BUFFER
hex "memory address of the TTB buffer"
default 0x02058000
config TTB_SIZE
hex "size of the TTB buffer"
default 0x4000
config SYS_SDRAM_BASE
hex
default 0x20000000

15
src/cpu/samsung/exynos5420/bootblock.c
View file

@ -17,10 +17,17 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/cache.h>
#include "clk.h"
#include "wakeup.h"
#include "cpu.h"
/* convenient shorthand (in MB) */
#define SRAM_START (0x02020000 >> 20)
#define SRAM_SIZE 1
#define SRAM_END (SRAM_START + SRAM_SIZE) /* plus one... */
void bootblock_cpu_init(void);
void bootblock_cpu_init(void)
{
@ -51,6 +58,14 @@ void bootblock_cpu_init(void)
/* Never returns. */
}
/* set up dcache and MMU */
mmu_init();
mmu_config_range(0, SRAM_START, DCACHE_OFF);
mmu_config_range(SRAM_START, SRAM_SIZE, DCACHE_WRITEBACK);
mmu_config_range(SRAM_END, 4096 - SRAM_END, DCACHE_OFF);
dcache_invalidate_all();
dcache_mmu_enable();
/* For most ARM systems, we have to initialize firmware media source
* (ex, SPI, SD/MMC, or eMMC) now; but for Exynos platform, that is
* already handled by iROM so there's no need to setup again.