diff --git a/src/soc/intel/broadwell/romstage/systemagent.c b/src/soc/intel/broadwell/romstage/systemagent.c
index 3384463122..8e4d82c74a 100644
--- a/src/soc/intel/broadwell/romstage/systemagent.c
+++ b/src/soc/intel/broadwell/romstage/systemagent.c
@@ -18,94 +18,38 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#include <stdint.h>
 #include <stdlib.h>
-#include <console/console.h>
 #include <arch/io.h>
 #include <device/pci_def.h>
-#include <elog.h>
-#include "haswell.h"
+#include <reg_script.h>
+#include <broadwell/iomap.h>
+#include <broadwell/pci_devs.h>
+#include <broadwell/romstage.h>
+#include <broadwell/systemagent.h>
 
-static void haswell_setup_bars(void)
-{
-	printk(BIOS_DEBUG, "Setting up static northbridge registers...");
-	/* Set up all hardcoded northbridge BARs */
-	pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
-	pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32);
-	pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
-	pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+DEFAULT_MCHBAR) >> 32);
-	pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1);
-	pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+DEFAULT_DMIBAR) >> 32);
+static const struct reg_script systemagent_early_init_script[] = {
+	REG_PCI_WRITE32(MCHBAR, MCH_BASE_ADDRESS | 1),
+	REG_PCI_WRITE32(DMIBAR, DMI_BASE_ADDRESS | 1),
+	REG_PCI_WRITE32(EPBAR, EP_BASE_ADDRESS | 1),
+	REG_MMIO_WRITE32(MCH_BASE_ADDRESS + EDRAMBAR, EDRAM_BASE_ADDRESS | 1),
+	REG_MMIO_WRITE32(MCH_BASE_ADDRESS + GDXCBAR, GDXC_BASE_ADDRESS | 1),
 
 	/* Set C0000-FFFFF to access RAM on both reads and writes */
-	pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30);
-	pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33);
-	pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33);
-	pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33);
-	pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33);
-	pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33);
-	pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33);
+	REG_PCI_WRITE8(PAM0, 0x30),
+	REG_PCI_WRITE8(PAM1, 0x33),
+	REG_PCI_WRITE8(PAM2, 0x33),
+	REG_PCI_WRITE8(PAM3, 0x33),
+	REG_PCI_WRITE8(PAM4, 0x33),
+	REG_PCI_WRITE8(PAM5, 0x33),
+	REG_PCI_WRITE8(PAM6, 0x33),
 
-	printk(BIOS_DEBUG, " done.\n");
-}
+	/* Device enable: IGD and Mini-HD */
+	REG_PCI_WRITE32(DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN),
 
-static void haswell_setup_graphics(void)
+	REG_SCRIPT_END
+};
+
+void systemagent_early_init(void)
 {
-	u32 reg32;
-	u16 reg16;
-	u8 reg8;
-
-	printk(BIOS_DEBUG, "Initializing Graphics...\n");
-
-	/* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
-	reg16 = pci_read_config16(PCI_DEV(0,0,0), GGC);
-	reg16 &= ~0x00f8;
-	reg16 |= 1 << 3;
-	/* Program GTT memory by setting GGC[9:8] = 2MB */
-	reg16 &= ~0x0300;
-	reg16 |= 2 << 8;
-	/* Enable VGA decode */
-	reg16 &= ~0x0002;
-	pci_write_config16(PCI_DEV(0,0,0), GGC, reg16);
-
-	/* Enable 256MB aperture */
-	reg8 = pci_read_config8(PCI_DEV(0, 2, 0), MSAC);
-	reg8 &= ~0x06;
-	reg8 |= 0x02;
-	pci_write_config8(PCI_DEV(0, 2, 0), MSAC, reg8);
-
-	/* Erratum workarounds */
-	reg32 = MCHBAR32(0x5f00);
-	reg32 |= (1 << 9)|(1 << 10);
-	MCHBAR32(0x5f00) = reg32;
-
-	/* Enable SA Clock Gating */
-	reg32 = MCHBAR32(0x5f00);
-	MCHBAR32(0x5f00) = reg32 | 1;
-
-	/* GPU RC6 workaround for sighting 366252 */
-	reg32 = MCHBAR32(0x5d14);
-	reg32 |= (1 << 31);
-	MCHBAR32(0x5d14) = reg32;
-
-	/* VLW */
-	reg32 = MCHBAR32(0x6120);
-	reg32 &= ~(1 << 0);
-	MCHBAR32(0x6120) = reg32;
-
-	reg32 = MCHBAR32(0x5418);
-	reg32 |= (1 << 4) | (1 << 5);
-	MCHBAR32(0x5418) = reg32;
-}
-
-void haswell_early_initialization(int chipset_type)
-{
-	/* Setup all BARs required for early PCIe and raminit */
-	haswell_setup_bars();
-
-	/* Device Enable: IGD and Mini-HD Audio */
-	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN,
-			   DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN);
-
-	haswell_setup_graphics();
+	reg_script_run_on_dev(SA_DEV_ROOT, systemagent_early_init_script);
 }