diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk index baa176f882..eefdae1f41 100644 --- a/src/soc/mediatek/mt8189/Makefile.mk +++ b/src/soc/mediatek/mt8189/Makefile.mk @@ -12,6 +12,7 @@ all-y += ../common/uart.c bootblock-y += bootblock.c bootblock-y += ../common/mmu_operations.c bootblock-y += ../common/mtcmos.c mtcmos.c +bootblock-y += ../common/pll.c pll.c bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c romstage-y += ../common/cbmem.c @@ -20,6 +21,7 @@ romstage-y += ../common/dramc_param.c romstage-y += ../common/emi.c romstage-y += ../common/memory.c ../common/memory_test.c romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +romstage-y += ../common/pll.c pll.c ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c ramstage-y += ../common/dramc_info.c diff --git a/src/soc/mediatek/mt8189/bootblock.c b/src/soc/mediatek/mt8189/bootblock.c index 0c55272cbe..8465a4974f 100644 --- a/src/soc/mediatek/mt8189/bootblock.c +++ b/src/soc/mediatek/mt8189/bootblock.c @@ -2,6 +2,7 @@ #include #include +#include #include #include @@ -9,5 +10,7 @@ void bootblock_soc_init(void) { mtk_mmu_init(); mtk_wdt_init(); + mt_pll_init(); mtcmos_init(); + mt_pll_post_init(); } diff --git a/src/soc/mediatek/mt8189/include/soc/addressmap.h b/src/soc/mediatek/mt8189/include/soc/addressmap.h index 826945347a..c02f25accd 100644 --- a/src/soc/mediatek/mt8189/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8189/include/soc/addressmap.h @@ -4,7 +4,15 @@ #define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_ADDRESSMAP_H__ enum { - IO_PHYS = 0x10000000, + MCUCFG_BASE = 0x0C530000, + DBGAO_BASE = 0x0D01A000, + DEM_BASE = 0x0D0A0000, + IO_PHYS = 0x10000000, +}; + +enum { + CPU_PLLDIV_CTRL_BASE = MCUCFG_BASE + 0x0000A2A0, + BUS_PLLDIV_CTRL_BASE = MCUCFG_BASE + 0x0000A2E0, }; enum { @@ -21,7 +29,7 @@ enum { GPIO_BASE = IO_PHYS + 0x00005000, APMIXED_BASE = IO_PHYS + 0x0000C000, DEVAPC_INFRA_SECU_AO_BASE = IO_PHYS + 0x0001C000, - BCRM_INFRA_AO_BASE = IO_PHYS + 0x00022000, + INFRA_AO_BCRM_BASE = IO_PHYS + 0x00022000, DEVAPC_INFRA_AO_BASE = IO_PHYS + 0x00030000, DEVAPC_INFRA_AO1_BASE = IO_PHYS + 0x00034000, EMI0_BASE = IO_PHYS + 0x00219000, @@ -37,10 +45,14 @@ enum { DPM_CFG_BASE2 = IO_PHYS + 0x00A40000, UART0_BASE = IO_PHYS + 0x01001000, SFLASH_REG_BASE = IO_PHYS + 0x01018000, + PERI_AO_BCRM_BASE = IO_PHYS + 0x01035000, PERICFG_AO_BASE = IO_PHYS + 0x01036000, DEVAPC_PERI_PAR_AO_BASE = IO_PHYS + 0x0103C000, + AUDIO_BASE = IO_PHYS + 0x01050000, SSUSB_IPPC_BASE = IO_PHYS + 0x01263E00, UFSHCI_BASE = IO_PHYS + 0x012B0000, + UFS0_AO_CFG_BASE = IO_PHYS + 0x012B8000, + UFS0_PDN_CFG_BASE = IO_PHYS + 0x012BB000, I2C0_DMA_BASE = IO_PHYS + 0x01300200, I2C1_DMA_BASE = IO_PHYS + 0x01300300, I2C2_DMA_BASE = IO_PHYS + 0x01300400, @@ -52,6 +64,7 @@ enum { I2C8_DMA_BASE = IO_PHYS + 0x01300A00, SSUSB_SIF_BASE = IO_PHYS + 0x01B00300, I2C2_BASE = IO_PHYS + 0x01B20000, + IMP_IIC_WRAP_WS_BASE = IO_PHYS + 0x01B21000, MIPITX0_BASE = IO_PHYS + 0x01B40000, IOCFG_LM_BASE = IO_PHYS + 0x01B50000, EDP_BASE = IO_PHYS + 0x01B70000, @@ -63,26 +76,49 @@ enum { I2C6_BASE = IO_PHYS + 0x01D73000, I2C7_BASE = IO_PHYS + 0x01F30000, I2C8_BASE = IO_PHYS + 0x01F31000, + IMP_IIC_WRAP_E_BASE = IO_PHYS + 0x01C22000, IOCFG_RB0_BASE = IO_PHYS + 0x01C50000, IOCFG_RB1_BASE = IO_PHYS + 0x01C60000, IOCFG_BM0_BASE = IO_PHYS + 0x01D20000, IOCFG_BM1_BASE = IO_PHYS + 0x01D30000, IOCFG_BM2_BASE = IO_PHYS + 0x01D40000, + IMP_IIC_WRAP_S_BASE = IO_PHYS + 0x01D74000, IOCFG_LT0_BASE = IO_PHYS + 0x01E20000, IOCFG_LT1_BASE = IO_PHYS + 0x01E30000, IOCFG_RT_BASE = IO_PHYS + 0x01F20000, + IMP_IIC_WRAP_EN_BASE = IO_PHYS + 0x01F32000, + MFGCFG_BASE = IO_PHYS + 0x03FBF000, + MMSYS_CONFIG_BASE = IO_PHYS + 0x04000000, DSI0_BASE = IO_PHYS + 0x04016000, DISP_DVO0 = IO_PHYS + 0x04019000, + IMGSYS1_BASE = IO_PHYS + 0x05020000, + IMGSYS2_BASE = IO_PHYS + 0x05820000, + VDEC_CORE_BASE = IO_PHYS + 0x0602F000, + VENC_GCON_BASE = IO_PHYS + 0x07000000, + CAMSYS_MAIN_BASE = IO_PHYS + 0x0A000000, + CAMSYS_RAWA_BASE = IO_PHYS + 0x0A04F000, + CAMSYS_RAWB_BASE = IO_PHYS + 0x0A06F000, + IPE_BASE = IO_PHYS + 0x0B000000, + VLPCFG_AO_REG_BASE = IO_PHYS + 0x0C000000, SPM_BASE = IO_PHYS + 0x0C001000, RGU_BASE = IO_PHYS + 0x0C00A000, VLPCFG_REG_BASE = IO_PHYS + 0x0C00C000, + DVFSRC_TOP_BASE = IO_PHYS + 0x0C00F000, + VLP_CK_BASE = IO_PHYS + 0x0C012000, SPMI_MST_BASE = IO_PHYS + 0x0C013000, DEVAPC_VLP_AO_BASE = IO_PHYS + 0x0C018000, + SCP_IIC_BASE = IO_PHYS + 0x0C80A000, + SCP_BASE = IO_PHYS + 0x0CB21000, SPMI_MST_P_BASE = IO_PHYS + 0x0CC00000, PMIF_SPMI_BASE = IO_PHYS + 0x0CC04000, PMIF_SPMI_P_BASE = IO_PHYS + 0x0CC06000, SYSTIMER_BASE = IO_PHYS + 0x0CC10000, + VAD_BASE = IO_PHYS + 0x0E010000, DEVAPC_MM_AO_BASE = IO_PHYS + 0x0E820000, + MMINFRA_CONFIG_BASE = IO_PHYS + 0x0E800000, + GCE_BASE = IO_PHYS + 0x0E980000, + MDP_GCE_BASE = IO_PHYS + 0x0E990000, + MDPSYS_CONFIG_BASE = IO_PHYS + 0x0F000000, }; #endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_ADDRESSMAP_H__ */ diff --git a/src/soc/mediatek/mt8189/include/soc/pll.h b/src/soc/mediatek/mt8189/include/soc/pll.h index 8d6de12dd1..fb8069c010 100644 --- a/src/soc/mediatek/mt8189/include/soc/pll.h +++ b/src/soc/mediatek/mt8189/include/soc/pll.h @@ -8,16 +8,548 @@ #ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_PLL_H__ #define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_PLL_H__ +#include #include -/* top_div rate */ -enum { - CLK26M_HZ = 26 * MHz, +static struct mtk_infra_ao_bcrm_regs *const + mtk_infra_ao_bcrm = (void *)INFRA_AO_BCRM_BASE; +static struct mtk_cpu_plldiv_cfg_regs *const + mtk_cpu_plldiv_cfg = (void *)CPU_PLLDIV_CTRL_BASE; +static struct mtk_bus_plldiv_cfg_regs *const + mtk_bus_plldiv_cfg = (void *)BUS_PLLDIV_CTRL_BASE; +static struct mtk_peri_ao_bcrm_regs *const + mtk_peri_ao_bcrm = (void *)PERI_AO_BCRM_BASE; +static struct mtk_vlp_regs *const + mtk_vlpsys = (void *)VLP_CK_BASE; +static struct mtk_pericfg_ao_regs *const + mtk_pericfg_ao = (void *)PERICFG_AO_BASE; +static struct mtk_afe_regs *const + mtk_afe = (void *)AUDIO_BASE; +static struct mtk_ufscfg_ao_regs *const + mtk_ufscfg_ao = (void *)UFS0_AO_CFG_BASE; +static struct mtk_ufscfg_pdn_regs *const + mtk_ufscfg_pdn = (void *)UFS0_PDN_CFG_BASE; +static struct mtk_imp_iic_wrap_ws_regs *const + mtk_imp_iic_wrap_ws = (void *)IMP_IIC_WRAP_WS_BASE; +static struct mtk_imp_iic_wrap_e_regs *const + mtk_imp_iic_wrap_e = (void *)IMP_IIC_WRAP_E_BASE; +static struct mtk_imp_iic_wrap_s_regs *const + mtk_imp_iic_wrap_s = (void *)IMP_IIC_WRAP_S_BASE; +static struct mtk_imp_iic_wrap_en_regs *const + mtk_imp_iic_wrap_en = (void *)IMP_IIC_WRAP_EN_BASE; +static struct mtk_mfg_regs *const + mtk_mfg = (void *)MFGCFG_BASE; +static struct mtk_mmsys_config_regs *const + mtk_mmsys_config = (void *)MMSYS_CONFIG_BASE; +static struct mtk_imgsys1_regs *const + mtk_imgsys1 = (void *)IMGSYS1_BASE; +static struct mtk_imgsys2_regs *const + mtk_imgsys2 = (void *)IMGSYS2_BASE; +static struct mtk_vdec_core_regs *const + mtk_vdec_core = (void *)VDEC_CORE_BASE; +static struct mtk_venc_gcon_regs *const + mtk_venc_gcon = (void *)VENC_GCON_BASE; +static struct mtk_scp_iic_regs *const + mtk_scp_iic = (void *)SCP_IIC_BASE; +static struct mtk_scp_regs *const + mtk_scp = (void *)SCP_BASE; +static struct mtk_vadsys_regs *const + mtk_vadsys = (void *)VAD_BASE; +static struct mtk_camsys_main_regs *const + mtk_camsys_main = (void *)CAMSYS_MAIN_BASE; +static struct mtk_camsys_rawa_regs *const + mtk_camsys_rawa = (void *)CAMSYS_RAWA_BASE; +static struct mtk_camsys_rawb_regs *const + mtk_camsys_rawb = (void *)CAMSYS_RAWB_BASE; +static struct mtk_ipesys_regs *const + mtk_ipesys = (void *)IPE_BASE; +static struct mtk_vlpcfg_ao_regs *const + mtk_vlpcfg_ao = (void *)VLPCFG_AO_REG_BASE; +static struct mtk_dvfsrc_top_regs *const + mtk_dvfsrc_top = (void *)DVFSRC_TOP_BASE; +static struct mtk_mminfra_config_regs *const + mtk_mminfra_config = (void *)MMINFRA_CONFIG_BASE; +static struct mtk_gce_d_regs *const + mtk_gce_d = (void *)GCE_BASE; +static struct mtk_gce_m_regs *const + mtk_gce_m = (void *)MDP_GCE_BASE; +static struct mtk_mdpsys_config_regs *const + mtk_mdpsys_config = (void *)MDPSYS_CONFIG_BASE; +static struct mtk_dbgao_regs *const + mtk_dbgao = (void *)DBGAO_BASE; +static struct mtk_dem_regs *const + mtk_dem = (void *)DEM_BASE; + +struct mtk_infra_ao_bcrm_regs { + u32 reserved[14]; + u32 vdnr_dcm_infra_par_bus_ctrl_0; +}; +check_member(mtk_infra_ao_bcrm_regs, vdnr_dcm_infra_par_bus_ctrl_0, 0x0038); + +struct mtk_cpu_plldiv_cfg_regs { + u32 cpu_plldiv_0_cfg0; + u32 cpu_plldiv_1_cfg0; }; -/* top_mux rate */ -enum { - UART_HZ = CLK26M_HZ, +struct mtk_bus_plldiv_cfg_regs { + u32 bus_plldiv_cfg0; }; +struct mtk_peri_ao_bcrm_regs { + u32 reserved1[8]; + u32 vdnr_dcm_peri_par_bus_ctrl_0; + u32 reserved2[8]; +}; +check_member(mtk_peri_ao_bcrm_regs, vdnr_dcm_peri_par_bus_ctrl_0, 0x0020); + +struct mtk_clk_cfg { + u32 cfg; + u32 set; + u32 clr; + u32 reserved; +}; + +struct mtk_vlp_clk_cfg { + u32 cfg; + u32 set; + u32 clr; +}; + +struct mtk_vlp_regs { + u32 reserved1; + u32 vlp_clk_cfg_update; + struct mtk_vlp_clk_cfg vlp_clk_cfg[6]; + u32 reserved2[104]; + u32 vlp_clk_cfg_30; + u32 vlp_clk_cfg_30_set; + u32 vlp_clk_cfg_30_clr; + u32 reserved3[13]; + u32 vlp_fqmtr_con[2]; +}; + +check_member(mtk_vlp_regs, vlp_clk_cfg_update, 0x0004); +check_member(mtk_vlp_regs, vlp_clk_cfg[0].set, 0x000C); +check_member(mtk_vlp_regs, vlp_clk_cfg[0].clr, 0x0010); +check_member(mtk_vlp_regs, vlp_clk_cfg[5].set, 0x0048); +check_member(mtk_vlp_regs, vlp_clk_cfg[5].clr, 0x004C); +check_member(mtk_vlp_regs, vlp_clk_cfg_30, 0x01F0); +check_member(mtk_vlp_regs, vlp_fqmtr_con[0], 0x0230); + +struct mtk_topckgen_regs { + u32 reserved1; + u32 clk_cfg_update[3]; + struct mtk_clk_cfg clk_cfg[17]; + u32 reserved2[8]; + u32 clk_misc_cfg_0; + u32 reserved3[7]; + u32 clk_mem_dfs_cfg; + u32 reserved4[6]; + u32 clk_dbg_cfg; + struct mtk_clk_cfg clk_cfg_17; + struct mtk_clk_cfg clk_cfg_18; + u32 reserved5[24]; + u32 clk_scp_cfg_0; + u32 reserved6[7]; + u32 clk26cali[2]; + u32 reserved7[6]; + struct mtk_clk_cfg clk_cfg_19; + u32 reserved8[176]; + struct mtk_clk_cfg clk_misc_cfg_3; +}; +check_member(mtk_topckgen_regs, clk_cfg_update[0], 0x0004); +check_member(mtk_topckgen_regs, clk_cfg[0].set, 0x0014); +check_member(mtk_topckgen_regs, clk_cfg[0].clr, 0x0018); +check_member(mtk_topckgen_regs, clk_cfg[16].set, 0x0114); +check_member(mtk_topckgen_regs, clk_cfg[16].clr, 0x0118); +check_member(mtk_topckgen_regs, clk_misc_cfg_0, 0x0140); +check_member(mtk_topckgen_regs, clk_mem_dfs_cfg, 0x0160); +check_member(mtk_topckgen_regs, clk_dbg_cfg, 0x017C); +check_member(mtk_topckgen_regs, clk_cfg_17.set, 0x0184); +check_member(mtk_topckgen_regs, clk_cfg_17.clr, 0x0188); +check_member(mtk_topckgen_regs, clk_cfg_18.set, 0x0194); +check_member(mtk_topckgen_regs, clk_cfg_18.clr, 0x0198); +check_member(mtk_topckgen_regs, clk_scp_cfg_0, 0x0200); +check_member(mtk_topckgen_regs, clk26cali, 0x0220); +check_member(mtk_topckgen_regs, clk_cfg_19.set, 0x0244); +check_member(mtk_topckgen_regs, clk_cfg_19.clr, 0x0248); +check_member(mtk_topckgen_regs, clk_misc_cfg_3.cfg, 0x0510); +check_member(mtk_topckgen_regs, clk_misc_cfg_3.set, 0x0514); +check_member(mtk_topckgen_regs, clk_misc_cfg_3.clr, 0x0518); + +struct mtk_apmixed_regs { + u32 reserved1[16]; + u32 apll1_tuner_con0; /* 0x0040 */ + u32 apll2_tuner_con0; + u32 reserved2[11]; + u32 pllen_all_set; /* 0x0074 */ + u32 pllen_all_clr; + u32 reserved3[2]; + u32 pll_div_rstb_all_set; /* 0x0084 */ + u32 reserved4[95]; + u32 armpll_ll_con[2]; /* 0x0204 */ + u32 reserved5[2]; + u32 armpll_bl_con[2]; /* 0x0214 */ + u32 reserved6[2]; + u32 ccipll_con[2]; /* 0x0224 */ + u32 reserved7[54]; + u32 mainpll_con[2]; /* 0x0304 */ + u32 reserved8[2]; + u32 univpll_con[2]; /* 0x0314 */ + u32 reserved9[2]; + u32 mmpll_con[2]; /* 0x0324 */ + u32 reserved10[2]; + u32 emipll_con[2]; /* 0x0334 */ + u32 reserved11[50]; + u32 apll1_con[3]; /* 0x0404 */ + u32 reserved12[2]; + u32 apll2_con[3]; /* 0x0418 */ + u32 reserved13[2]; + u32 tvdpll1_con[2]; /* 0x042c */ + u32 reserved14[2]; + u32 tvdpll2_con[2]; /* 0x043c */ + u32 reserved15[48]; + u32 mfgpll_con[2]; /* 0x0504 */ + u32 reserved16[2]; + u32 ethpll_con[2]; /* 0x0514 */ + u32 reserved17[2]; + u32 msdcpll_con[2]; /* 0x0524 */ + u32 reserved18[2]; + u32 ufspll_con[2]; /* 0x0534 */ + u32 reserved19[50]; + u32 apupll_con[2]; /* 0x0604 */ + u32 reserved20[2]; + u32 apupll2_con[2]; /* 0x0614 */ + u32 reserved21[57]; + u32 ap_clksq_con0; /* 0x0700 */ +}; +check_member(mtk_apmixed_regs, apll1_tuner_con0, 0x0040); +check_member(mtk_apmixed_regs, pllen_all_set, 0x0074); +check_member(mtk_apmixed_regs, pll_div_rstb_all_set, 0x0084); +check_member(mtk_apmixed_regs, armpll_ll_con[0], 0x0204); +check_member(mtk_apmixed_regs, armpll_bl_con[0], 0x0214); +check_member(mtk_apmixed_regs, ccipll_con[0], 0x0224); +check_member(mtk_apmixed_regs, mainpll_con[0], 0x0304); +check_member(mtk_apmixed_regs, univpll_con[0], 0x0314); +check_member(mtk_apmixed_regs, mmpll_con[0], 0x0324); +check_member(mtk_apmixed_regs, emipll_con[0], 0x0334); +check_member(mtk_apmixed_regs, apll1_con[0], 0x0404); +check_member(mtk_apmixed_regs, apll2_con[0], 0x0418); +check_member(mtk_apmixed_regs, tvdpll1_con[0], 0x042C); +check_member(mtk_apmixed_regs, tvdpll2_con[0], 0x043C); +check_member(mtk_apmixed_regs, mfgpll_con[0], 0x0504); +check_member(mtk_apmixed_regs, ethpll_con[0], 0x0514); +check_member(mtk_apmixed_regs, msdcpll_con[0], 0x0524); +check_member(mtk_apmixed_regs, ufspll_con[0], 0x0534); +check_member(mtk_apmixed_regs, apupll_con[0], 0x0604); +check_member(mtk_apmixed_regs, apupll2_con[0], 0x0614); +check_member(mtk_apmixed_regs, ap_clksq_con0, 0x0700); + +struct mtk_pericfg_ao_regs { + u32 reserved1[4]; + u32 pericfg_ao_peri_cg_0; + u32 pericfg_ao_peri_cg_1; + u32 pericfg_ao_peri_cg_2; + u32 reserved2[2]; + u32 pericfg_ao_peri_cg_0_set; + u32 pericfg_ao_peri_cg_0_clr; + u32 pericfg_ao_peri_cg_1_set; + u32 pericfg_ao_peri_cg_1_clr; + u32 pericfg_ao_peri_cg_2_set; + u32 pericfg_ao_peri_cg_2_clr; +}; +check_member(mtk_pericfg_ao_regs, pericfg_ao_peri_cg_0, 0x0010); +check_member(mtk_pericfg_ao_regs, pericfg_ao_peri_cg_0_set, 0x0024); + +struct mtk_afe_regs { + u32 audio_audio_top[5]; +}; + +struct mtk_ufscfg_ao_regs { + u32 reserved1; + u32 ufscfg_ao_reg_ufs_ao_cg_0; + u32 ufscfg_ao_reg_ufs_ao_cg_0_set; + u32 ufscfg_ao_reg_ufs_ao_cg_0_clr; +}; + +struct mtk_ufscfg_pdn_regs { + u32 reserved1; + u32 ufscfg_pdn_reg_ufs_pdn_cg_0; + u32 ufscfg_pdn_reg_ufs_pdn_cg_0_set; + u32 ufscfg_pdn_reg_ufs_pdn_cg_0_clr; +}; + +struct mtk_imp_iic_wrap_ws_regs { + u32 reserved1[896]; + u32 imp_iic_wrap_ws_ap_clock_cg; + u32 imp_iic_wrap_ws_ap_clock_cg_clr; + u32 imp_iic_wrap_ws_ap_clock_cg_set; +}; +check_member(mtk_imp_iic_wrap_ws_regs, imp_iic_wrap_ws_ap_clock_cg, 0x0E00); + +struct mtk_imp_iic_wrap_e_regs { + u32 reserved1[896]; + u32 imp_iic_wrap_e_ap_clock_cg; + u32 imp_iic_wrap_e_ap_clock_cg_clr; + u32 imp_iic_wrap_e_ap_clock_cg_set; +}; +check_member(mtk_imp_iic_wrap_e_regs, imp_iic_wrap_e_ap_clock_cg, 0x0E00); + +struct mtk_imp_iic_wrap_s_regs { + u32 reserved1[896]; + u32 imp_iic_wrap_s_ap_clock_cg; + u32 imp_iic_wrap_s_ap_clock_cg_clr; + u32 imp_iic_wrap_s_ap_clock_cg_set; +}; +check_member(mtk_imp_iic_wrap_s_regs, imp_iic_wrap_s_ap_clock_cg, 0x0E00); + +struct mtk_imp_iic_wrap_en_regs { + u32 reserved1[896]; + u32 imp_iic_wrap_en_ap_clock_cg; + u32 imp_iic_wrap_en_ap_clock_cg_clr; + u32 imp_iic_wrap_en_ap_clock_cg_set; +}; +check_member(mtk_imp_iic_wrap_en_regs, imp_iic_wrap_en_ap_clock_cg, 0x0E00); + +struct mtk_mfg_regs { + u32 mfg_mfg_cg_con; + u32 mfg_mfg_cg_con_set; + u32 mfg_mfg_cg_con_clr; +}; + +struct mtk_mmsys_config_regs { + u32 reserved1[64]; + u32 mmsys_config_mmsys_cg_0; + u32 mmsys_config_mmsys_cg_0_set; + u32 mmsys_config_mmsys_cg_0_clr; + u32 reserved2[1]; + u32 mmsys_config_mmsys_cg_1; + u32 mmsys_config_mmsys_cg_1_set; + u32 mmsys_config_mmsys_cg_1_clr; +}; +check_member(mtk_mmsys_config_regs, mmsys_config_mmsys_cg_0, 0x0100); +check_member(mtk_mmsys_config_regs, mmsys_config_mmsys_cg_1, 0x0110); + +struct mtk_imgsys1_regs { + u32 imgsys1_img_cg; + u32 imgsys1_img_cg_set; + u32 imgsys1_img_cg_clr; +}; + +struct mtk_imgsys2_regs { + u32 imgsys2_img_cg; + u32 imgsys2_img_cg_set; + u32 imgsys2_img_cg_clr; +}; + +struct mtk_vdec_core_regs { + u32 vdec_core_vdec_cken; + u32 vdec_core_vdec_cken_clr; + u32 vdec_core_larb_cken_con; + u32 vdec_core_larb_cken_con_clr; +}; + +struct mtk_venc_gcon_regs { + u32 venc_gcon_vencsys_cg; + u32 venc_gcon_vencsys_cg_set; + u32 venc_gcon_vencsys_cg_clr; +}; + +struct mtk_scp_iic_regs { + u32 reserved[900]; + u32 scp_iic_ccu_clock_cg; + u32 scp_iic_ccu_clock_cg_clr; + u32 scp_iic_ccu_clock_cg_set; +}; +check_member(mtk_scp_iic_regs, scp_iic_ccu_clock_cg, 0x0E10); + +struct mtk_scp_regs { + u32 reserved[85]; + u32 scp_ap_spi_cg; + u32 scp_ap_spi_cg_clr; +}; +check_member(mtk_scp_regs, scp_ap_spi_cg, 0x0154); + +struct mtk_vadsys_regs { + u32 vad_vadsys_ck_en; + u32 reserved1[95]; + u32 vad_vow_audiodsp_sw_cg; +}; +check_member(mtk_vadsys_regs, vad_vow_audiodsp_sw_cg, 0x0180); + +struct mtk_camsys_main_regs { + u32 camsys_main_camsys_cg; + u32 camsys_main_camsys_cg_set; + u32 camsys_main_camsys_cg_clr; +}; + +struct mtk_camsys_rawa_regs { + u32 camsys_rawa_camsys_cg; + u32 camsys_rawa_camsys_cg_set; + u32 camsys_rawa_camsys_cg_clr; +}; + +struct mtk_camsys_rawb_regs { + u32 camsys_rawb_camsys_cg; + u32 camsys_rawb_camsys_cg_set; + u32 camsys_rawb_camsys_cg_clr; +}; + +struct mtk_ipesys_regs { + u32 ipe_img_cg; + u32 ipe_img_cg_set; + u32 ipe_img_cg_clr; +}; + +struct mtk_vlpcfg_ao_regs { + u32 reserved[512]; + u32 vlpcfg_ao_reg_debugtop_vlpao_ctrl; +}; +check_member(mtk_vlpcfg_ao_regs, vlpcfg_ao_reg_debugtop_vlpao_ctrl, 0x0800); + +struct mtk_dvfsrc_top_regs { + u32 dvfsrc_top_dvfsrc_basic_control; +}; + +struct mtk_mminfra_config_regs { + u32 reserved1[64]; + u32 mminfra_config_mminfra_cg_0; + u32 mminfra_config_mminfra_cg_0_set; + u32 mminfra_config_mminfra_cg_0_clr; + u32 reserved2[1]; + u32 mminfra_config_mminfra_cg_1; + u32 mminfra_config_mminfra_cg_1_set; + u32 mminfra_config_mminfra_cg_1_clr; +}; +check_member(mtk_mminfra_config_regs, mminfra_config_mminfra_cg_0, 0x0100); +check_member(mtk_mminfra_config_regs, mminfra_config_mminfra_cg_1, 0x0110); + +struct mtk_gce_d_regs { + u32 reserved[60]; + u32 gce_gce_ctl_int0; +}; +check_member(mtk_gce_d_regs, gce_gce_ctl_int0, 0x00F0); + +struct mtk_gce_m_regs { + u32 reserved[60]; + u32 mdp_gce_gce_ctl_int0; +}; +check_member(mtk_gce_m_regs, mdp_gce_gce_ctl_int0, 0x00F0); + +struct mtk_mdpsys_config_regs { + u32 reserved1[64]; + u32 mdpsys_config_mdpsys_cg_0; + u32 mdpsys_config_mdpsys_cg_0_set; + u32 mdpsys_config_mdpsys_cg_0_clr; + u32 reserved2[1]; + u32 mdpsys_config_mdpsys_cg_1; + u32 mdpsys_config_mdpsys_cg_1_set; + u32 mdpsys_config_mdpsys_cg_1_clr; +}; +check_member(mtk_mdpsys_config_regs, mdpsys_config_mdpsys_cg_0, 0x0100); +check_member(mtk_mdpsys_config_regs, mdpsys_config_mdpsys_cg_1, 0x0110); + +struct mtk_dbgao_regs { + u32 reserved[28]; + u32 dbgao_atb; +}; +check_member(mtk_dbgao_regs, dbgao_atb, 0x0070); + +struct mtk_dem_regs { + u32 reserved1[11]; + u32 dem_dbgbusclk_en; + u32 dem_dbgsysclk_en; + u32 reserved2[15]; + u32 dem_atb; +}; +check_member(mtk_dem_regs, dem_dbgbusclk_en, 0x002C); +check_member(mtk_dem_regs, dem_atb, 0x0070); + +/* Fmeter Type */ +enum fmeter_id { + APLL1_CTRL, + APLL2_CTRL, + ARMPLL_BL_CTRL, + ARMPLL_LL_CTRL, + CCIPLL_CTRL, + MAINPLL_CTRL, + MMPLL_CTRL, + MSDCPLL_CTRL, + UFSPLL_CTRL, + UNIVPLL_CTRL, + EMIPLL_CTRL, + TVDPLL1_CTRL, + TVDPLL2_CTRL, + MFGPLL_CTRL, + ETHPLL_CTRL, + APUPLL_CTRL, + APUPLL2_CTRL, + VLP_CKSYS_TOP_CTRL, +}; + +/* PLL set rate list */ +enum pll_rate_type { + ARMPLL_LL_RATE = 0, + ARMPLL_BL_RATE, + CCIPLL_RATE, + PLL_RATE_NUM, +}; + +#define ARMPLL_BL_ID 6 +#define ARMPLL_LL_ID 8 +#define CCIPLL_ID 10 + +enum { + ARMPLL_LL_HZ = 1600UL * MHz, + ARMPLL_BL_HZ = 1700UL * MHz, + CCIPLL_HZ = 1140UL * MHz, + MAINPLL_HZ = 2184UL * MHz, + UNIVPLL_HZ = 2496UL * MHz, + MMPLL_HZ = 2750UL * MHz, + MFGPLL_HZ = 390 * MHz, + APLL1_HZ = 180633600UL, + APLL2_HZ = 196608UL * KHz, + EMIPLL_HZ = 387 * MHz, + APUPLL2_HZ = 230 * MHz, + APUPLL_HZ = 330 * MHz, + TVDPLL1_HZ = 594 * MHz, + TVDPLL2_HZ = 594 * MHz, + ETHPLL_HZ = 500 * MHz, + MSDCPLL_HZ = 416 * MHz, + UFSPLL_HZ = 594 * MHz, +}; + +enum { + CLK26M_HZ = 26 * MHz, + UNIVPLL_D6_D2_HZ = UNIVPLL_HZ / 6 / 2, +}; + +enum { + PCW_INTEGER_BITS = 8, +}; + +enum { + SPI_HZ = UNIVPLL_D6_D2_HZ, + UART_HZ = CLK26M_HZ, +}; + +enum { + PLL_EN_DELAY = 20, +}; + +enum { + MCU_DIV_MASK = 0x1f << 17, + MCU_DIV_1 = 0x8 << 17, + + MCU_MUX_MASK = 0x3 << 9, + MCU_MUX_SRC_PLL = 0x1 << 9, + MCU_MUX_SRC_26M = 0x0 << 9, +}; + +/* + * Clock manager functions + */ +void mt_pll_post_init(void); +u32 mt_get_vlpck_freq(u32 id); +void mt_set_topck_default(void); + #endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_PLL_H__ */ diff --git a/src/soc/mediatek/mt8189/pll.c b/src/soc/mediatek/mt8189/pll.c new file mode 100644 index 0000000000..24c7cc59e9 --- /dev/null +++ b/src/soc/mediatek/mt8189/pll.c @@ -0,0 +1,727 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * This file is created based on MT8189 Functional Specification + * Chapter number: 8.1 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define VLP_FM_WAIT_TIME 40 + +enum mux_id { + CLK_TOP_AXI_SEL, + CLK_TOP_AXI_PERI_SEL, + CLK_TOP_AXI_U_SEL, + CLK_TOP_BUS_AXIMEM_SEL, + CLK_TOP_DISP0_SEL, + CLK_TOP_MMINFRA_SEL, + CLK_TOP_UART_SEL, + CLK_TOP_SPI0_SEL, + CLK_TOP_SPI1_SEL, + CLK_TOP_SPI2_SEL, + CLK_TOP_SPI3_SEL, + CLK_TOP_SPI4_SEL, + CLK_TOP_SPI5_SEL, + CLK_TOP_MSDC_MACRO_0P_SEL, + CLK_TOP_MSDC50_0_HCLK_SEL, + CLK_TOP_MSDC50_0_SEL, + CLK_TOP_AES_MSDCFDE_SEL, + CLK_TOP_MSDC_MACRO_1P_SEL, + CLK_TOP_MSDC30_1_SEL, + CLK_TOP_MSDC30_1_HCLK_SEL, + CLK_TOP_MSDC_MACRO_2P_SEL, + CLK_TOP_MSDC30_2_SEL, + CLK_TOP_MSDC30_2_HCLK_SEL, + CLK_TOP_AUD_INTBUS_SEL, + CLK_TOP_ATB_SEL, + CLK_TOP_DISP_PWM_SEL, + CLK_TOP_USB_TOP_P0_SEL, + CLK_TOP_USB_XHCI_P0_SEL, + CLK_TOP_USB_TOP_P1_SEL, + CLK_TOP_USB_XHCI_P1_SEL, + CLK_TOP_USB_TOP_P2_SEL, + CLK_TOP_USB_XHCI_P2_SEL, + CLK_TOP_USB_TOP_P3_SEL, + CLK_TOP_USB_XHCI_P3_SEL, + CLK_TOP_USB_TOP_P4_SEL, + CLK_TOP_USB_XHCI_P4_SEL, + CLK_TOP_I2C_SEL, + CLK_TOP_AUD_ENGEN1_SEL, + CLK_TOP_AUD_ENGEN2_SEL, + CLK_TOP_AES_UFSFDE_SEL, + CLK_TOP_U_SEL, + CLK_TOP_U_MBIST_SEL, + CLK_TOP_AUD_1_SEL, + CLK_TOP_AUD_2_SEL, + CLK_TOP_PWM_SEL, + CLK_TOP_AUDIO_H_SEL, + CLK_TOP_MCUPM_SEL, + CLK_TOP_MEM_SUB_SEL, + CLK_TOP_MEM_SUB_U_SEL, + CLK_TOP_DXCC_SEL, + CLK_TOP_DP_SEL, + CLK_TOP_EDP_SEL, + CLK_TOP_EDP_FAVT_SEL, + CLK_TOP_SFLASH_SEL, + CLK_TOP_ECC_SEL, + CLK_TOP_APLL_I2SIN0_MCK_SEL, + CLK_TOP_APLL_I2SIN1_MCK_SEL, + CLK_TOP_APLL_I2SIN4_MCK_SEL, + CLK_TOP_APLL_I2SOUT0_MCK_SEL, + CLK_TOP_APLL_I2SOUT1_MCK_SEL, + CLK_TOP_APLL_I2SOUT4_MCK_SEL, + CLK_TOP_APLL_TDMOUT_MCK_SEL, +}; + +enum vlp_mux_id { + CLK_VLP_CK_SCP_SEL, + CLK_VLP_CK_PWRAP_ULPOSC_SEL, + CLK_VLP_CK_SPMI_P_MST_SEL, + CLK_VLP_CK_DVFSRC_SEL, + CLK_VLP_CK_PWM_VLP_SEL, + CLK_VLP_CK_AXI_VLP_SEL, + CLK_VLP_CK_SYSTIMER_26M_SEL, + CLK_VLP_CK_SSPM_SEL, + CLK_VLP_CK_SSPM_F26M_SEL, + CLK_VLP_CK_SRCK_SEL, + CLK_VLP_CK_SCP_SPI_SEL, + CLK_VLP_CK_SCP_IIC_SEL, + CLK_VLP_CK_SCP_SPI_HIGH_SPD_SEL, + CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL, + CLK_VLP_CK_SSPM_ULPOSC_SEL, + CLK_VLP_CK_APXGPT_26M_SEL, + CLK_VLP_CK_AUD_ADC_SEL, + CLK_VLP_CK_KP_IRQ_GEN_SEL +}; + +struct mux_sel { + u8 id; + u8 sel; +}; + +struct vlp_mux_sel { + u8 id; + u8 sel; +}; + +#define MUX(_id, _sys, _clk_cfg, _mux_shift, _mux_width)\ + [_id] = { \ + .reg = &_sys->_clk_cfg.cfg, \ + .set_reg = &_sys->_clk_cfg.set, \ + .clr_reg = &_sys->_clk_cfg.clr, \ + .mux_shift = _mux_shift, \ + .mux_width = _mux_width, \ + } + +#define MUX_UPD(_id, _sys, _clk_cfg, _mux_shift, _mux_width, _upd_reg, _upd_shift)\ + [_id] = { \ + .reg = &_sys->_clk_cfg.cfg, \ + .set_reg = &_sys->_clk_cfg.set, \ + .clr_reg = &_sys->_clk_cfg.clr, \ + .mux_shift = _mux_shift, \ + .mux_width = _mux_width, \ + .upd_reg = &_sys->_upd_reg, \ + .upd_shift = _upd_shift, \ + } + +#define CKSYS_MUX(_id, _clk_cfg, _mux_shift, _mux_width)\ + MUX(_id, mtk_topckgen, _clk_cfg, _mux_shift, _mux_width) + +#define CKSYS_MUX_UPD(_id, _clk_cfg, _mux_shift, _mux_width, _upd_reg, _upd_shift)\ + MUX_UPD(_id, mtk_topckgen, _clk_cfg, _mux_shift, _mux_width, _upd_reg, _upd_shift) + +#define VLP_MUX_UPD(_id, _clk_cfg, _mux_shift, _mux_width, _upd_shift)\ + MUX_UPD(_id, mtk_vlpsys, _clk_cfg, _mux_shift, _mux_width, vlp_clk_cfg_update, \ + _upd_shift) + +static const struct mux muxes[] = { + CKSYS_MUX_UPD(CLK_TOP_AXI_SEL, clk_cfg[0], 0, 3, clk_cfg_update[0], 0), + CKSYS_MUX_UPD(CLK_TOP_AXI_PERI_SEL, clk_cfg[0], 8, 2, clk_cfg_update[0], 1), + CKSYS_MUX_UPD(CLK_TOP_AXI_U_SEL, clk_cfg[0], 16, 2, clk_cfg_update[0], 2), + CKSYS_MUX_UPD(CLK_TOP_BUS_AXIMEM_SEL, clk_cfg[0], 24, 3, clk_cfg_update[0], 3), + CKSYS_MUX_UPD(CLK_TOP_DISP0_SEL, clk_cfg[1], 0, 4, clk_cfg_update[0], 4), + CKSYS_MUX_UPD(CLK_TOP_MMINFRA_SEL, clk_cfg[1], 8, 4, clk_cfg_update[0], 5), + CKSYS_MUX_UPD(CLK_TOP_UART_SEL, clk_cfg[1], 16, 1, clk_cfg_update[0], 6), + CKSYS_MUX_UPD(CLK_TOP_SPI0_SEL, clk_cfg[1], 24, 3, clk_cfg_update[0], 7), + CKSYS_MUX_UPD(CLK_TOP_SPI1_SEL, clk_cfg[2], 0, 3, clk_cfg_update[0], 8), + CKSYS_MUX_UPD(CLK_TOP_SPI2_SEL, clk_cfg[2], 8, 3, clk_cfg_update[0], 9), + CKSYS_MUX_UPD(CLK_TOP_SPI3_SEL, clk_cfg[2], 16, 3, clk_cfg_update[0], 10), + CKSYS_MUX_UPD(CLK_TOP_SPI4_SEL, clk_cfg[2], 24, 3, clk_cfg_update[0], 11), + CKSYS_MUX_UPD(CLK_TOP_SPI5_SEL, clk_cfg[3], 0, 3, clk_cfg_update[0], 12), + CKSYS_MUX_UPD(CLK_TOP_MSDC_MACRO_0P_SEL, clk_cfg[3], 8, 2, clk_cfg_update[0], 13), + CKSYS_MUX_UPD(CLK_TOP_MSDC50_0_HCLK_SEL, clk_cfg[3], 16, 2, clk_cfg_update[0], 14), + CKSYS_MUX_UPD(CLK_TOP_MSDC50_0_SEL, clk_cfg[3], 24, 3, clk_cfg_update[0], 15), + CKSYS_MUX_UPD(CLK_TOP_AES_MSDCFDE_SEL, clk_cfg[4], 0, 3, clk_cfg_update[0], 16), + CKSYS_MUX_UPD(CLK_TOP_MSDC_MACRO_1P_SEL, clk_cfg[4], 8, 2, clk_cfg_update[0], 17), + CKSYS_MUX_UPD(CLK_TOP_MSDC30_1_SEL, clk_cfg[4], 16, 3, clk_cfg_update[0], 18), + CKSYS_MUX_UPD(CLK_TOP_MSDC30_1_HCLK_SEL, clk_cfg[4], 24, 2, clk_cfg_update[0], 19), + CKSYS_MUX_UPD(CLK_TOP_MSDC_MACRO_2P_SEL, clk_cfg[5], 0, 2, clk_cfg_update[0], 20), + CKSYS_MUX_UPD(CLK_TOP_MSDC30_2_SEL, clk_cfg[5], 8, 3, clk_cfg_update[0], 21), + CKSYS_MUX_UPD(CLK_TOP_MSDC30_2_HCLK_SEL, clk_cfg[5], 16, 2, clk_cfg_update[0], 22), + CKSYS_MUX_UPD(CLK_TOP_AUD_INTBUS_SEL, clk_cfg[5], 24, 2, clk_cfg_update[0], 23), + CKSYS_MUX_UPD(CLK_TOP_ATB_SEL, clk_cfg[6], 0, 2, clk_cfg_update[0], 24), + CKSYS_MUX_UPD(CLK_TOP_DISP_PWM_SEL, clk_cfg[6], 8, 3, clk_cfg_update[0], 25), + CKSYS_MUX_UPD(CLK_TOP_USB_TOP_P0_SEL, clk_cfg[6], 16, 2, clk_cfg_update[0], 26), + CKSYS_MUX_UPD(CLK_TOP_USB_XHCI_P0_SEL, clk_cfg[6], 24, 2, clk_cfg_update[0], 27), + CKSYS_MUX_UPD(CLK_TOP_USB_TOP_P1_SEL, clk_cfg[7], 0, 2, clk_cfg_update[0], 28), + CKSYS_MUX_UPD(CLK_TOP_USB_XHCI_P1_SEL, clk_cfg[7], 8, 2, clk_cfg_update[0], 29), + CKSYS_MUX_UPD(CLK_TOP_USB_TOP_P2_SEL, clk_cfg[7], 16, 2, clk_cfg_update[0], 30), + CKSYS_MUX_UPD(CLK_TOP_USB_XHCI_P2_SEL, clk_cfg[7], 24, 2, clk_cfg_update[1], 0), + CKSYS_MUX_UPD(CLK_TOP_USB_TOP_P3_SEL, clk_cfg[8], 0, 2, clk_cfg_update[1], 1), + CKSYS_MUX_UPD(CLK_TOP_USB_XHCI_P3_SEL, clk_cfg[8], 8, 2, clk_cfg_update[1], 2), + CKSYS_MUX_UPD(CLK_TOP_USB_TOP_P4_SEL, clk_cfg[8], 16, 2, clk_cfg_update[1], 3), + CKSYS_MUX_UPD(CLK_TOP_USB_XHCI_P4_SEL, clk_cfg[8], 24, 2, clk_cfg_update[1], 4), + CKSYS_MUX_UPD(CLK_TOP_I2C_SEL, clk_cfg[9], 0, 2, clk_cfg_update[1], 5), + CKSYS_MUX_UPD(CLK_TOP_AUD_ENGEN1_SEL, clk_cfg[9], 24, 2, clk_cfg_update[1], 8), + CKSYS_MUX_UPD(CLK_TOP_AUD_ENGEN2_SEL, clk_cfg[10], 0, 2, clk_cfg_update[1], 9), + CKSYS_MUX_UPD(CLK_TOP_AES_UFSFDE_SEL, clk_cfg[10], 8, 3, clk_cfg_update[1], 10), + CKSYS_MUX_UPD(CLK_TOP_U_SEL, clk_cfg[10], 16, 3, clk_cfg_update[1], 11), + CKSYS_MUX_UPD(CLK_TOP_U_MBIST_SEL, clk_cfg[10], 24, 2, clk_cfg_update[1], 12), + CKSYS_MUX_UPD(CLK_TOP_AUD_1_SEL, clk_cfg[11], 0, 1, clk_cfg_update[1], 13), + CKSYS_MUX_UPD(CLK_TOP_AUD_2_SEL, clk_cfg[11], 8, 1, clk_cfg_update[1], 14), + CKSYS_MUX_UPD(CLK_TOP_PWM_SEL, clk_cfg[12], 0, 1, clk_cfg_update[1], 17), + CKSYS_MUX_UPD(CLK_TOP_AUDIO_H_SEL, clk_cfg[12], 8, 2, clk_cfg_update[1], 18), + CKSYS_MUX_UPD(CLK_TOP_MCUPM_SEL, clk_cfg[12], 16, 2, clk_cfg_update[1], 19), + CKSYS_MUX_UPD(CLK_TOP_MEM_SUB_SEL, clk_cfg[12], 24, 4, clk_cfg_update[1], 20), + CKSYS_MUX_UPD(CLK_TOP_MEM_SUB_U_SEL, clk_cfg[13], 8, 3, clk_cfg_update[1], 22), + CKSYS_MUX_UPD(CLK_TOP_DXCC_SEL, clk_cfg[15], 24, 2, clk_cfg_update[2], 1), + CKSYS_MUX_UPD(CLK_TOP_DP_SEL, clk_cfg[16], 16, 3, clk_cfg_update[2], 4), + CKSYS_MUX_UPD(CLK_TOP_EDP_SEL, clk_cfg[16], 24, 3, clk_cfg_update[2], 5), + CKSYS_MUX_UPD(CLK_TOP_EDP_FAVT_SEL, clk_cfg_17, 0, 3, clk_cfg_update[2], 6), + CKSYS_MUX_UPD(CLK_TOP_SFLASH_SEL, clk_cfg_18, 0, 3, clk_cfg_update[2], 10), + CKSYS_MUX_UPD(CLK_TOP_ECC_SEL, clk_cfg_19, 8, 3, clk_cfg_update[2], 15), +}; + +static const struct mux_sel mux_sels[] = { + { .id = CLK_TOP_AXI_SEL, .sel = 2 }, + { .id = CLK_TOP_AXI_PERI_SEL, .sel = 2 }, + { .id = CLK_TOP_AXI_U_SEL, .sel = 2 }, + { .id = CLK_TOP_BUS_AXIMEM_SEL, .sel = 2 }, + { .id = CLK_TOP_DISP0_SEL, .sel = 11 }, + { .id = CLK_TOP_MMINFRA_SEL, .sel = 14 }, + { .id = CLK_TOP_UART_SEL, .sel = 1 }, + { .id = CLK_TOP_SPI0_SEL, .sel = 1 }, + { .id = CLK_TOP_SPI1_SEL, .sel = 1 }, + { .id = CLK_TOP_SPI2_SEL, .sel = 1 }, + { .id = CLK_TOP_SPI3_SEL, .sel = 1 }, + { .id = CLK_TOP_SPI4_SEL, .sel = 1 }, + { .id = CLK_TOP_SPI5_SEL, .sel = 1 }, + { .id = CLK_TOP_MSDC_MACRO_0P_SEL, .sel = 1 }, + { .id = CLK_TOP_MSDC50_0_HCLK_SEL, .sel = 1 }, + { .id = CLK_TOP_MSDC50_0_SEL, .sel = 1 }, + { .id = CLK_TOP_AES_MSDCFDE_SEL, .sel = 4 }, + { .id = CLK_TOP_MSDC_MACRO_1P_SEL, .sel = 1 }, + { .id = CLK_TOP_MSDC30_1_SEL, .sel = 4 }, + { .id = CLK_TOP_MSDC30_1_HCLK_SEL, .sel = 1 }, + { .id = CLK_TOP_MSDC_MACRO_2P_SEL, .sel = 1 }, + { .id = CLK_TOP_MSDC30_2_SEL, .sel = 4 }, + { .id = CLK_TOP_MSDC30_2_HCLK_SEL, .sel = 1 }, + { .id = CLK_TOP_AUD_INTBUS_SEL, .sel = 1 }, + { .id = CLK_TOP_ATB_SEL, .sel = 1 }, + { .id = CLK_TOP_DISP_PWM_SEL, .sel = 6 }, + { .id = CLK_TOP_USB_TOP_P0_SEL, .sel = 1 }, + { .id = CLK_TOP_USB_XHCI_P0_SEL, .sel = 1 }, + { .id = CLK_TOP_USB_TOP_P1_SEL, .sel = 1 }, + { .id = CLK_TOP_USB_XHCI_P1_SEL, .sel = 1 }, + { .id = CLK_TOP_USB_TOP_P2_SEL, .sel = 1 }, + { .id = CLK_TOP_USB_XHCI_P2_SEL, .sel = 1 }, + { .id = CLK_TOP_USB_TOP_P3_SEL, .sel = 1 }, + { .id = CLK_TOP_USB_XHCI_P3_SEL, .sel = 1 }, + { .id = CLK_TOP_USB_TOP_P4_SEL, .sel = 1 }, + { .id = CLK_TOP_USB_XHCI_P4_SEL, .sel = 1 }, + { .id = CLK_TOP_I2C_SEL, .sel = 2 }, + { .id = CLK_TOP_AUD_ENGEN1_SEL, .sel = 2 }, + { .id = CLK_TOP_AUD_ENGEN2_SEL, .sel = 2 }, + { .id = CLK_TOP_AES_UFSFDE_SEL, .sel = 1 }, + { .id = CLK_TOP_U_SEL, .sel = 5 }, + { .id = CLK_TOP_U_MBIST_SEL, .sel = 3 }, + { .id = CLK_TOP_AUD_1_SEL, .sel = 1 }, + { .id = CLK_TOP_AUD_2_SEL, .sel = 1 }, + { .id = CLK_TOP_PWM_SEL, .sel = 0 }, + { .id = CLK_TOP_AUDIO_H_SEL, .sel = 3 }, + { .id = CLK_TOP_MCUPM_SEL, .sel = 2 }, + { .id = CLK_TOP_MEM_SUB_SEL, .sel = 9 }, + { .id = CLK_TOP_MEM_SUB_U_SEL, .sel = 7 }, + { .id = CLK_TOP_DXCC_SEL, .sel = 1 }, + { .id = CLK_TOP_DP_SEL, .sel = 4 }, + { .id = CLK_TOP_EDP_SEL, .sel = 4 }, + { .id = CLK_TOP_EDP_FAVT_SEL, .sel = 4 }, + { .id = CLK_TOP_SFLASH_SEL, .sel = 0 }, + { .id = CLK_TOP_ECC_SEL, .sel = 5 }, +}; + +static const struct mux vlp_muxes[] = { + VLP_MUX_UPD(CLK_VLP_CK_SCP_SEL, vlp_clk_cfg[0], 0, 4, 0), + VLP_MUX_UPD(CLK_VLP_CK_PWRAP_ULPOSC_SEL, vlp_clk_cfg[0], 8, 3, 1), + VLP_MUX_UPD(CLK_VLP_CK_SPMI_P_MST_SEL, vlp_clk_cfg[0], 16, 4, 2), + VLP_MUX_UPD(CLK_VLP_CK_DVFSRC_SEL, vlp_clk_cfg[0], 24, 1, 3), + VLP_MUX_UPD(CLK_VLP_CK_PWM_VLP_SEL, vlp_clk_cfg[1], 0, 3, 4), + VLP_MUX_UPD(CLK_VLP_CK_AXI_VLP_SEL, vlp_clk_cfg[1], 8, 3, 5), + VLP_MUX_UPD(CLK_VLP_CK_SYSTIMER_26M_SEL, vlp_clk_cfg[1], 16, 1, 6), + VLP_MUX_UPD(CLK_VLP_CK_SSPM_SEL, vlp_clk_cfg[1], 24, 3, 7), + VLP_MUX_UPD(CLK_VLP_CK_SSPM_F26M_SEL, vlp_clk_cfg[2], 0, 1, 8), + VLP_MUX_UPD(CLK_VLP_CK_SRCK_SEL, vlp_clk_cfg[2], 8, 1, 9), + VLP_MUX_UPD(CLK_VLP_CK_SCP_SPI_SEL, vlp_clk_cfg[2], 16, 2, 10), + VLP_MUX_UPD(CLK_VLP_CK_SCP_IIC_SEL, vlp_clk_cfg[2], 24, 2, 11), + VLP_MUX_UPD(CLK_VLP_CK_SCP_SPI_HIGH_SPD_SEL, vlp_clk_cfg[3], 0, 2, 12), + VLP_MUX_UPD(CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL, vlp_clk_cfg[3], 8, 2, 13), + VLP_MUX_UPD(CLK_VLP_CK_SSPM_ULPOSC_SEL, vlp_clk_cfg[3], 16, 2, 14), + VLP_MUX_UPD(CLK_VLP_CK_APXGPT_26M_SEL, vlp_clk_cfg[3], 24, 1, 15), + VLP_MUX_UPD(CLK_VLP_CK_AUD_ADC_SEL, vlp_clk_cfg[5], 16, 2, 22), + VLP_MUX_UPD(CLK_VLP_CK_KP_IRQ_GEN_SEL, vlp_clk_cfg[5], 24, 3, 23), +}; + +static const struct vlp_mux_sel vlp_mux_sels[] = { + { .id = CLK_VLP_CK_SCP_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_PWRAP_ULPOSC_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_SPMI_P_MST_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_DVFSRC_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_PWM_VLP_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_AXI_VLP_SEL, .sel = 4 }, + { .id = CLK_VLP_CK_SYSTIMER_26M_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_SSPM_SEL, .sel = 4 }, + { .id = CLK_VLP_CK_SSPM_F26M_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_SRCK_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_SCP_SPI_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_SCP_IIC_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_SCP_SPI_HIGH_SPD_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_SSPM_ULPOSC_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_APXGPT_26M_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_AUD_ADC_SEL, .sel = 1 }, + { .id = CLK_VLP_CK_KP_IRQ_GEN_SEL, .sel = 4 } +}; + +enum pll_id { + CLK_APMIXED_ARMPLL_LL, + CLK_APMIXED_ARMPLL_BL, + CLK_APMIXED_CCIPLL, + CLK_APMIXED_MAINPLL, + CLK_APMIXED_UNIVPLL, + CLK_APMIXED_MMPLL, + CLK_APMIXED_MFGPLL, + CLK_APMIXED_APLL1, + CLK_APMIXED_APLL2, + CLK_APMIXED_EMIPLL, + CLK_APMIXED_APUPLL2, + CLK_APMIXED_APUPLL, + CLK_APMIXED_TVDPLL1, + CLK_APMIXED_TVDPLL2, + CLK_APMIXED_ETHPLL, + CLK_APMIXED_MSDCPLL, + CLK_APMIXED_UFSPLL +}; + +struct rate { + u8 id; /* enum pll_id */ + u32 rate; +}; + +static const struct rate pll_rates[] = { + { CLK_APMIXED_ARMPLL_LL, ARMPLL_LL_HZ }, + { CLK_APMIXED_ARMPLL_BL, ARMPLL_BL_HZ }, + { CLK_APMIXED_CCIPLL, CCIPLL_HZ }, + { CLK_APMIXED_MAINPLL, MAINPLL_HZ }, + { CLK_APMIXED_UNIVPLL, UNIVPLL_HZ }, + { CLK_APMIXED_MMPLL, MMPLL_HZ }, + { CLK_APMIXED_MFGPLL, MFGPLL_HZ }, + { CLK_APMIXED_APLL1, APLL1_HZ }, + { CLK_APMIXED_APLL2, APLL2_HZ }, + { CLK_APMIXED_EMIPLL, EMIPLL_HZ }, + { CLK_APMIXED_APUPLL2, APUPLL2_HZ }, + { CLK_APMIXED_APUPLL, APUPLL_HZ }, + { CLK_APMIXED_TVDPLL1, TVDPLL1_HZ }, + { CLK_APMIXED_TVDPLL2, TVDPLL2_HZ }, + { CLK_APMIXED_ETHPLL, ETHPLL_HZ }, + { CLK_APMIXED_MSDCPLL, MSDCPLL_HZ }, + { CLK_APMIXED_UFSPLL, UFSPLL_HZ } +}; + +static const u32 pll_div_rate[] = { + 3800UL * MHz, + 1900 * MHz, + 950 * MHz, + 475 * MHz, + 237500 * KHz, + 0, +}; + +#define PLL_SYS(_id, _reg, _rstb, _pcwbits, _div_reg, _div_shift, \ + _pcw_reg, _pcw_shift, _div_rate) \ + [_id] = { \ + .reg = &mtk_apmixed->_reg, \ + .rstb_shift = _rstb, \ + .pcwbits = _pcwbits, \ + .div_reg = &mtk_apmixed->_div_reg, \ + .div_shift = _div_shift, \ + .pcw_reg = &mtk_apmixed->_pcw_reg, \ + .pcw_shift = _pcw_shift, \ + .div_rate = _div_rate, \ + } + +static const struct pll plls[] = { + PLL_SYS(CLK_APMIXED_ARMPLL_LL, armpll_ll_con[0], NO_RSTB_SHIFT, 22, + armpll_ll_con[1], 24, armpll_ll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_ARMPLL_BL, armpll_bl_con[0], NO_RSTB_SHIFT, 22, + armpll_bl_con[1], 24, armpll_bl_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_CCIPLL, ccipll_con[0], NO_RSTB_SHIFT, 22, + ccipll_con[1], 24, ccipll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_MAINPLL, mainpll_con[0], 23, 22, + mainpll_con[1], 24, mainpll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_UNIVPLL, univpll_con[0], 23, 22, + univpll_con[1], 24, univpll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_MMPLL, mmpll_con[0], 23, 22, + mmpll_con[1], 24, mmpll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_MFGPLL, mfgpll_con[0], NO_RSTB_SHIFT, 22, + mfgpll_con[1], 24, mfgpll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_APLL1, apll1_con[0], NO_RSTB_SHIFT, 32, + apll1_con[1], 24, apll1_con[2], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_APLL2, apll2_con[0], NO_RSTB_SHIFT, 32, + apll2_con[1], 24, apll2_con[2], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_EMIPLL, emipll_con[0], NO_RSTB_SHIFT, 22, + emipll_con[1], 24, emipll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_APUPLL2, apupll2_con[0], NO_RSTB_SHIFT, 22, + apupll2_con[1], 24, apupll2_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_APUPLL, apupll_con[0], NO_RSTB_SHIFT, 22, + apupll_con[1], 24, apupll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_TVDPLL1, tvdpll1_con[0], NO_RSTB_SHIFT, 22, + tvdpll1_con[1], 24, tvdpll1_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_TVDPLL2, tvdpll2_con[0], NO_RSTB_SHIFT, 22, + tvdpll2_con[1], 24, tvdpll2_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_ETHPLL, ethpll_con[0], NO_RSTB_SHIFT, 22, + ethpll_con[1], 24, ethpll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_MSDCPLL, msdcpll_con[0], NO_RSTB_SHIFT, 22, + msdcpll_con[1], 24, msdcpll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_UFSPLL, ufspll_con[0], NO_RSTB_SHIFT, 22, + ufspll_con[1], 24, ufspll_con[1], 0, pll_div_rate), +}; + +struct pll_reg_list { + const char *name; + void *div_reg; + void *con0; + void *con1; +}; + +struct fmeter_data { + u8 id; + void *pll_con0; + void *pll_con1; + void *con0; + void *con1; +}; + +static const struct fmeter_data fmd[] = { + [APLL1_CTRL] = {APLL1_CTRL, &mtk_apmixed->apll1_con[0]}, + [APLL2_CTRL] = {APLL2_CTRL, &mtk_apmixed->apll2_con[0]}, + [ARMPLL_BL_CTRL] = {ARMPLL_BL_CTRL, &mtk_apmixed->armpll_bl_con[0]}, + [ARMPLL_LL_CTRL] = {ARMPLL_LL_CTRL, &mtk_apmixed->armpll_ll_con[0]}, + [CCIPLL_CTRL] = {CCIPLL_CTRL, &mtk_apmixed->ccipll_con[0]}, + [MAINPLL_CTRL] = {MAINPLL_CTRL, &mtk_apmixed->mainpll_con[0]}, + [MMPLL_CTRL] = {MMPLL_CTRL, &mtk_apmixed->mmpll_con[0]}, + [MSDCPLL_CTRL] = {MSDCPLL_CTRL, &mtk_apmixed->msdcpll_con[0]}, + [UFSPLL_CTRL] = {UFSPLL_CTRL, &mtk_apmixed->ufspll_con[0]}, + [UNIVPLL_CTRL] = {UNIVPLL_CTRL, &mtk_apmixed->univpll_con[0]}, + [EMIPLL_CTRL] = {EMIPLL_CTRL, &mtk_apmixed->emipll_con[0]}, + [TVDPLL1_CTRL] = {TVDPLL1_CTRL, &mtk_apmixed->tvdpll1_con[0]}, + [TVDPLL2_CTRL] = {TVDPLL2_CTRL, &mtk_apmixed->tvdpll2_con[0]}, + [MFGPLL_CTRL] = {MFGPLL_CTRL, &mtk_apmixed->mfgpll_con[0]}, + [ETHPLL_CTRL] = {ETHPLL_CTRL, &mtk_apmixed->ethpll_con[0]}, + [APUPLL_CTRL] = {APUPLL_CTRL, &mtk_apmixed->apupll_con[0]}, + [APUPLL2_CTRL] = {APUPLL2_CTRL, &mtk_apmixed->apupll2_con[0]}, + [VLP_CKSYS_TOP_CTRL] = {VLP_CKSYS_TOP_CTRL, 0, 0, + &mtk_vlpsys->vlp_fqmtr_con[0], + &mtk_vlpsys->vlp_fqmtr_con[1]}, +}; + +static u32 mt_get_subsys_freq(const struct fmeter_data fm_data, u32 id) +{ + u32 output = 0, ckdiv_en = 0; + u32 temp; + + if (fm_data.pll_con0 != 0) { + /* check ckdiv_en */ + if (read32(fm_data.pll_con0) & 0x00010000) + ckdiv_en = 1; + /* pll con0[19] = 1, pll con0[16] = 1, pll con0[12] = 1 */ + /* select pll_ckdiv, enable pll_ckdiv, enable test clk */ + setbits32(fm_data.pll_con0, BIT(19) | BIT(16) | BIT(12)); + } + + /* CLK26CALI_0[15]: rst 1 -> 0 */ + write32(fm_data.con0, 0); + /* CLK26CALI_0[15]: rst 0 -> 1 */ + setbits32(fm_data.con0, BIT(15)); + + /* vlp freq meter sel ckgen[20:16] */ + /* other subsys freq meter sel ckgen[2:0] */ + if (fm_data.id == VLP_CKSYS_TOP_CTRL) + clrsetbits32(fm_data.con0, GENMASK(20, 16), id << 16); + else + clrsetbits32(fm_data.con0, GENMASK(2, 0), id); + + clrsetbits32(fm_data.con1, GENMASK(31, 16), 0x1FF << 16); + + /* select divider?dvt set zero */ + clrbits32(fm_data.con0, GENMASK(31, 24)); + + setbits32(fm_data.con0, BIT(12)); + setbits32(fm_data.con0, BIT(4)); + /* fmeter con0[1:0] = 0 */ + /* choose test clk */ + clrbits32(fm_data.con0, BIT(1) | BIT(0)); + + /* wait frequency meter finish */ + if (fm_data.id == VLP_CKSYS_TOP_CTRL) + udelay(VLP_FM_WAIT_TIME); + else + wait_us(1000, !(read32(fm_data.con0) & BIT(4))); + + temp = read32(fm_data.con1) & 0xFFFF; + output = ((temp * 26000)) / 512; /* Khz */ + + if (fm_data.pll_con0 != 0) { + /* pll con0[19] = 0, pll con0[12] = 0 */ + if (ckdiv_en) + clrbits32(fm_data.pll_con0, BIT(19) | BIT(12)); + else + clrbits32(fm_data.pll_con0, BIT(19) | BIT(16) | BIT(12)); + } + + write32(fm_data.con0, 0x8000); + + printk(BIOS_INFO, "subsys meter[%d:%d] = %d Khz\n", fm_data.id, id, output); + + return output; +} + +u32 mt_get_vlpck_freq(u32 id) +{ + return mt_get_subsys_freq(fmd[VLP_CKSYS_TOP_CTRL], id); +} + +void mt_set_topck_default(void) +{ + int i; + + write32(&mtk_topckgen->clk_cfg[0].clr, 0xFFFFFFF0); + for (i = 1; i <= 16; i++) + write32(&mtk_topckgen->clk_cfg[i].clr, 0xFFFFFFFF); + write32(&mtk_topckgen->clk_cfg_17.clr, 0xFFFFFFFF); + write32(&mtk_topckgen->clk_cfg_18.clr, 0xFFFFFFFF); + write32(&mtk_topckgen->clk_cfg_19.clr, 0xFFFFFFFF); + write32(&mtk_topckgen->clk_cfg_update[0], 0x7FFFFFFE); + write32(&mtk_topckgen->clk_cfg_update[1], 0x7FFFFFFF); + write32(&mtk_topckgen->clk_cfg_update[2], 0x0000FFFF); +} + +void pll_set_pcw_change(const struct pll *pll) +{ + setbits32(pll->div_reg, PLL_PCW_CHG); +} + +void mt_pll_init(void) +{ + int i; + + printk(BIOS_INFO, "Pll init start...\n"); + + spm_power_on(); + + printk(BIOS_INFO, "pll control start...\n"); + /* [0]=1 (CLKSQ_EN) + Default Value to avoid using BootROM's setting */ + setbits32(&mtk_apmixed->ap_clksq_con0, BIT(0)); + + /* Wait 100us */ + udelay(100); + + /* [2]=1 (CLKSQ_LPF_EN) */ + setbits32(&mtk_apmixed->ap_clksq_con0, BIT(2)); + + for (i = 0; i < ARRAY_SIZE(pll_rates); i++) + pll_set_rate(&plls[pll_rates[i].id], pll_rates[i].rate); + + write32(&mtk_apmixed->apll1_tuner_con0, 0x6F28BD4D); + write32(&mtk_apmixed->apll2_tuner_con0, 0x78FD5266); + setbits32(&mtk_apmixed->emipll_con[0], BIT(8)); + + /* PLL all enable */ + write32(&mtk_apmixed->pllen_all_set, 0x0007FFFC); + + /* Wait PLL stable (20us) */ + udelay(20); + + /* turn on pll div en */ + setbits32(&mtk_apmixed->mainpll_con[0], GENMASK(31, 24)); + setbits32(&mtk_apmixed->univpll_con[0], GENMASK(31, 24)); + udelay(20); + + /* pll all rstb */ + write32(&mtk_apmixed->pll_div_rstb_all_set, 0x00000007); + + printk(BIOS_INFO, "pll control done...\n"); + + /* [10:9] muxsel: switch to PLL speed */ + clrsetbits32(&mtk_cpu_plldiv_cfg->cpu_plldiv_0_cfg0, GENMASK(10, 9), BIT(9)); + + /* [10:9] muxsel: switch to PLL speed */ + clrsetbits32(&mtk_cpu_plldiv_cfg->cpu_plldiv_1_cfg0, GENMASK(10, 9), BIT(9)); + + /* [10:9] muxsel: switch to PLL speed */ + clrsetbits32(&mtk_bus_plldiv_cfg->bus_plldiv_cfg0, GENMASK(10, 9), BIT(9)); + + /* Infra DCM divider */ + setbits32(&mtk_infra_ao_bcrm->vdnr_dcm_infra_par_bus_ctrl_0, BIT(6) | BIT(3)); + + /* Peri DCM divider */ + setbits32(&mtk_peri_ao_bcrm->vdnr_dcm_peri_par_bus_ctrl_0, BIT(10) | BIT(7) | BIT(4)); + + printk(BIOS_INFO, "mux switch control start...\n"); + + for (i = 0; i < ARRAY_SIZE(mux_sels); i++) + pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); + + /* update mux */ + write32(&mtk_topckgen->clk_cfg_update[0], 0x7FFFFFFF); + write32(&mtk_topckgen->clk_cfg_update[1], 0x7FFFFFFF); + write32(&mtk_topckgen->clk_cfg_update[2], 0x0000FFFF); + + /* femisys_dvfs_ck_gfmux_sel = 1(emipll_ck) */ + write32(&mtk_topckgen->clk_mem_dfs_cfg, 0x1); + + for (i = 0; i < ARRAY_SIZE(vlp_mux_sels); i++) + pll_mux_set_sel(&vlp_muxes[vlp_mux_sels[i].id], vlp_mux_sels[i].sel); + + /* update mux */ + write32(&mtk_vlpsys->vlp_clk_cfg_update, 0x00FFFFFF); + + printk(BIOS_INFO, "mux switch control done...\n"); + + printk(BIOS_INFO, "Pll init Done!!\n"); +} + +void mt_pll_post_init(void) +{ + /* for CG */ + printk(BIOS_INFO, "subsysCG enable start...\n"); + + /* TOPCKGEN CG Clear */ + write32(&mtk_topckgen->clk_misc_cfg_3.clr, 0x00010000); + write32(&mtk_topckgen->clk_misc_cfg_3.set, 0xDF3CFCFF); + /* INFRACFG_AO CG Clear */ + write32(&mtk_infracfg_ao->infracfg_ao_module_cg_0_clr, 0x10000000); + write32(&mtk_infracfg_ao->infracfg_ao_module_cg_1_clr, 0x21000000); + write32(&mtk_infracfg_ao->infracfg_ao_module_cg_2_clr, 0x08000000); + write32(&mtk_infracfg_ao->infracfg_ao_module_cg_3_clr, 0x02000000); + /* PERICFG_AO CG Clear */ + write32(&mtk_pericfg_ao->pericfg_ao_peri_cg_0_clr, 0x3FFFFFFF); + write32(&mtk_pericfg_ao->pericfg_ao_peri_cg_1_clr, 0x3DBDFBF6); + write32(&mtk_pericfg_ao->pericfg_ao_peri_cg_2_clr, 0x0FFFFFFB); + /* UFSCFG_AO_REG CG Clear */ + write32(&mtk_ufscfg_ao->ufscfg_ao_reg_ufs_ao_cg_0_clr, 0x0000007F); + /* IMP_IIC_WRAP_WS CG Clear */ + write32(&mtk_imp_iic_wrap_ws->imp_iic_wrap_ws_ap_clock_cg_clr, 0x00000001); + /* IMP_IIC_WRAP_E CG Clear */ + write32(&mtk_imp_iic_wrap_e->imp_iic_wrap_e_ap_clock_cg_clr, 0x00000003); + /* IMP_IIC_WRAP_S CG Clear */ + write32(&mtk_imp_iic_wrap_s->imp_iic_wrap_s_ap_clock_cg_clr, 0x0000000F); + /* IMP_IIC_WRAP_EN CG Clear */ + write32(&mtk_imp_iic_wrap_en->imp_iic_wrap_en_ap_clock_cg_clr, 0x00000003); + /* VLP_CK CG Clear */ + write32(&mtk_vlpsys->vlp_clk_cfg_30_set, 0x00000832); + /* SCP_IIC CG Clear */ + write32(&mtk_scp_iic->scp_iic_ccu_clock_cg_set, 0x00000003); + /* SCP CG Clear */ + setbits32(&mtk_scp->scp_ap_spi_cg, BIT(1) | BIT(0)); + /* VLPCFG_AO_REG CG Clear */ + clrbits32(&mtk_vlpcfg_ao->vlpcfg_ao_reg_debugtop_vlpao_ctrl, BIT(8)); + /* VLPCFG_REG CG Clear */ + setbits32(&mtk_vlpcfg->vlp_test_ck_ctrl, + BIT(28) | BIT(24) | BIT(23) | BIT(22) | BIT(21) | BIT(20) | + BIT(18) | BIT(13) | BIT(12) | BIT(11) | BIT(10) | BIT(9) | + BIT(8) | BIT(7) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)); + /* DVFSRC_TOP CG Clear */ + setbits32(&mtk_dvfsrc_top->dvfsrc_top_dvfsrc_basic_control, BIT(0)); + + /* DBGAO CG Clear */ + setbits32(&mtk_dbgao->dbgao_atb, BIT(0)); + /* DEM CG Clear*/ + setbits32(&mtk_dem->dem_atb, BIT(0)); + setbits32(&mtk_dem->dem_dbgbusclk_en, BIT(0)); + setbits32(&mtk_dem->dem_dbgsysclk_en, BIT(0)); + /* UFSCFG_PDN_REG CG Clear */ + write32(&mtk_ufscfg_pdn->ufscfg_pdn_reg_ufs_pdn_cg_0_clr, 0x0000002B); + + /* MMINFRA_CONFIG CG Clear */ + write32(&mtk_mminfra_config->mminfra_config_mminfra_cg_0_clr, 0x00000007); + write32(&mtk_mminfra_config->mminfra_config_mminfra_cg_1_clr, 0x00020000); + /* GCE CG Clear */ + clrbits32(&mtk_gce_d->gce_gce_ctl_int0, BIT(16)); + + printk(BIOS_INFO, "subsysCG enable done...\n"); +} + +void mt_pll_raise_little_cpu_freq(u32 freq) +{ + /* switch clock source to intermediate clock */ + clrsetbits32(&mtk_cpu_plldiv_cfg->cpu_plldiv_0_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M); + + /* disable armpll_ll frequency output */ + write32(&mtk_apmixed->pllen_all_clr, 0x40000); + + /* raise armpll_ll frequency */ + pll_set_rate(&plls[CLK_APMIXED_ARMPLL_LL], freq); + + /* enable armpll_ll frequency output */ + write32(&mtk_apmixed->pllen_all_set, 0x40000); + udelay(PLL_EN_DELAY); + + /* switch clock source back to armpll_ll */ + clrsetbits32(&mtk_cpu_plldiv_cfg->cpu_plldiv_0_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); +} + +void mt_pll_raise_cci_freq(u32 freq) +{ + /* switch clock source to intermediate clock */ + clrsetbits32(&mtk_bus_plldiv_cfg->bus_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M); + + /* disable ccipll frequency output */ + write32(&mtk_apmixed->pllen_all_clr, 0x10000); + + /* raise ccipll frequency */ + pll_set_rate(&plls[CLK_APMIXED_CCIPLL], freq); + + /* enable ccipll frequency output */ + write32(&mtk_apmixed->pllen_all_set, 0x10000); + udelay(PLL_EN_DELAY); + + /* switch clock source back to ccipll */ + clrsetbits32(&mtk_bus_plldiv_cfg->bus_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); +} + +void mt_pll_set_tvd_pll1_freq(u32 freq) +{ + /* disable tvdpll frequency output */ + write32(&mtk_apmixed->pllen_all_clr, 0x200); + + /* set tvdpll frequency */ + pll_set_rate(&plls[CLK_APMIXED_TVDPLL2], freq); + + /* enable tvdpll frequency output */ + write32(&mtk_apmixed->pllen_all_set, 0x200); + udelay(PLL_EN_DELAY); +} + +void mt_pll_edp_mux_set_sel(u32 sel) +{ + pll_mux_set_sel(&muxes[CLK_TOP_EDP_SEL], sel); +}