From c1f98d46cf844e00648abd146e64ed8d44cc3316 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= <j.neuschaefer@gmx.net>
Date: Mon, 22 Aug 2016 19:37:15 +0200
Subject: [PATCH] UPSTREAM: arch/riscv: Enable U-mode/S-mode counters (stime,
 etc.)

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16262
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Change-Id: Ie62f60b2e237fa4921384e3894569ae29639f563
Reviewed-on: https://chromium-review.googlesource.com/374463
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
---
 src/arch/riscv/virtual_memory.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index 98b7edca4e..fab7d90d70 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -218,4 +218,8 @@ void mstatus_init(void)
 			| (1 << CAUSE_FAULT_STORE)
 			| (1 << CAUSE_USER_ECALL)
 	);
+
+	/* Enable all user/supervisor-mode counters */
+	write_csr(mscounteren, 0b111);
+	write_csr(mucounteren, 0b111);
 }