From c19c0f1d7cb3cb2635766c186ba9598933424a78 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Mon, 24 Feb 2014 07:56:31 -0800 Subject: [PATCH] baytrail: Disable P-state HW coordination on 4-core SKU The 4-core SKU needs to use SW_ALL for P-state coordination. There are related bits in MSR_POWER_MISC that need to be set based on whether or not hardware coordination is disabled. 2-core systems: - MSR_PMG_CST_CONFIG_CONTROL clear bit 11 - MSR_POWER_MISC set bit 2,3 - \_PR.CPUx._PSD coordination set to 0xFE (HW_ALL) 4-core systems: - MSR_PMG_CST_CONFIG_CONTROL set bit 11 - MSR_POWER_MISC clear bit 2,3 - \_PR.CPUx._PSD coordination set to 0xFC (SW_ALL) BUG=chrome-os-partner:26125 BRANCH=baytrail TEST=build and boot on (2-core) rambi. Check MSR and ACPI _PSD. Change-Id: I17e84dc50b4bcbffa599498b2bfeac43c135e5b4 Signed-off-by: Duncan Laurie Reviewed-on: https://chromium-review.googlesource.com/187575 Reviewed-by: Aaron Durbin --- src/soc/intel/baytrail/acpi.c | 5 +++-- src/soc/intel/baytrail/baytrail/msr.h | 3 +++ src/soc/intel/baytrail/cpu.c | 26 ++++++++++++++++++++++++++ 3 files changed, 32 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 70d50a0c29..67e8c0ca89 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -353,8 +353,9 @@ static int generate_P_state_entries(int core, int cores_per_package) vid_max = pattrs->iacore_vids[IACORE_MAX]; vid_min = pattrs->iacore_vids[IACORE_LFM]; - /* Hardware coordination of P-states */ - coord_type = HW_ALL; + /* Set P-states coordination type based on MSR disable bit */ + msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); + coord_type = (msr.lo & SINGLE_PCTL) ? SW_ALL : HW_ALL; /* Max Non-Turbo Frequency */ clock_max = (ratio_max * pattrs->bclk_khz) / 1000; diff --git a/src/soc/intel/baytrail/baytrail/msr.h b/src/soc/intel/baytrail/baytrail/msr.h index e6775ef25e..656d26aae7 100644 --- a/src/soc/intel/baytrail/baytrail/msr.h +++ b/src/soc/intel/baytrail/baytrail/msr.h @@ -24,7 +24,10 @@ #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd #define MSR_PLATFORM_INFO 0xce #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define SINGLE_PCTL (1 << 11) #define MSR_POWER_MISC 0x120 +#define ENABLE_ULFM_AUTOCM_MASK (1 << 2) +#define ENABLE_INDP_AUTOCM_MASK (1 << 3) #define MSR_IA32_PERF_CTL 0x199 #define MSR_IA32_MISC_ENABLES 0x1a0 #define MSR_POWER_CTL 0x1fc diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 217d7eaebb..9c678ccca7 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -75,6 +75,29 @@ const struct reg_script core_msr_script[] = { REG_SCRIPT_END }; +/* Enable hardware coordination for 2-core, disable for 4-core */ +static void baytrail_set_pstate_coord(void) +{ + const struct pattrs *pattrs = pattrs_get(); + msr_t pmg_cst = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); + msr_t power_misc = rdmsr(MSR_POWER_MISC); + + if (pattrs->num_cpus > 2) { + /* Disable hardware coordination */ + pmg_cst.lo |= SINGLE_PCTL; + power_misc.lo &= ~(ENABLE_ULFM_AUTOCM_MASK | + ENABLE_INDP_AUTOCM_MASK); + } else { + /* Enable hardware coordination */ + pmg_cst.lo &= ~SINGLE_PCTL; + power_misc.lo |= (ENABLE_ULFM_AUTOCM_MASK | + ENABLE_INDP_AUTOCM_MASK); + } + + wrmsr(MSR_PMG_CST_CONFIG_CONTROL, pmg_cst); + wrmsr(MSR_POWER_MISC, power_misc); +} + void baytrail_init_cpus(device_t dev) { struct bus *cpu_bus = dev->link_list; @@ -118,6 +141,9 @@ static void baytrail_core_init(device_t cpu) /* Set core MSRs */ reg_script_run(core_msr_script); + /* Set P-State coordination */ + baytrail_set_pstate_coord(); + /* Set this core to max frequency ratio */ set_max_freq(); }