From c189604f4335624967d32b59b72cdbd418e34a97 Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Thu, 30 Oct 2025 14:54:04 -0700 Subject: [PATCH] mb/goog/ocelot/var/ocelot: Enable rp5 if PCIE WiFi detected Enable rp5 if the FW_CONFIG bits for WIFI are set to WIFI_PCIE_6 or WIFI_PCIE_7. BUG=b:444509417 TEST=emerge-ocelot coreboot chromeos-bootimage', flash ocelot and verify CNVI and PCIe WiFi solutions are detected correctly. Change-Id: I077bfc48a82c354d1011ef756aa6aa55bf6951cd Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/89838 Tested-by: build bot (Jenkins) Reviewed-by: Appukuttan V K Reviewed-by: Karthik Ramasubramanian --- .../google/ocelot/variants/ocelot/overridetree.cb | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb index 7a06471ea3..3b0c1b49c7 100644 --- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb +++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb @@ -473,6 +473,16 @@ chip soc/intel/pantherlake end end # Gen4 M.2 SSD + device ref pcie_rp5 on + probe WIFI WIFI_PCIE_6 + probe WIFI WIFI_PCIE_7 + register "pcie_rp[PCIE_RP(5)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + end # M.2 WLAN KEY-E + device ref pcie_rp6 on probe SD SD_GENSYS probe SD SD_BAYHUB