From c15006eb0cf97d9b60c0ecc05beae610cf2efb40 Mon Sep 17 00:00:00 2001 From: Kilian Krause Date: Fri, 4 Jul 2025 10:59:48 +0200 Subject: [PATCH] soc/intel/alderlake: Add 28W TDP support for RPL-P ID 8 (0xa716) Add voltage regulator configuration for Intel Raptor Lake-P processor with MCH ID 0xa716 (RPL_P_ID_8) at 28W TDP. This processor has a 4+4 core configuration. - Add the MCH ID mapping to the 28W TDP processor variant - Add VR configurations for loadline, ICC, TDC timewindow, and TDC current limit tables The VR configuration is adapted from the existing 28W variants. TEST=Built and booted on hardware with MCH ID 0xa716. Verified resolution of "Unknown MCH" errors and correct power limit configuration. System boots successfully to OS. Before: [DEBUG] BS: BS_DEV_INIT_CHIPS entry times (exec / console): 649 / 543 ms [DEBUG] All HSPHY ports disabled, skipping HSPHY loading [INFO ] Disabling PCH PCIE ClockGating+PowerGating. [ERROR] Unknown MCH (0xa716) in load_table [ERROR] Unknown MCH (0xa716) in load_table [ERROR] Unknown MCH (0xa716) in load_table [ERROR] Unknown MCH (0xa716) in load_table [ERROR] Unknown MCH (0xa716) in load_table [ERROR] Unknown MCH (0xa716) in load_table [ERROR] Unknown MCH (0xa716) in load_table [ERROR] Unknown MCH (0xa716) in load_table [ERROR] Unknown MCH (0xa716) in load_table [ERROR] Unknown MCH (0xa716) in load_table [INFO ] PCI 1.0, PIN A, using IRQ #16 ... [DEBUG] BS: BS_DEV_ENABLE exit times (exec / console): 20 / 4 ms [INFO ] Initializing devices... [DEBUG] PCI: 00:00:00.0 init [ERROR] unknown SA ID: 0xa716, skipped power limits configuration. [DEBUG] PCI: 00:00:00.0 init finished in 7 msecs After: [DEBUG] BS: BS_DEV_INIT_CHIPS entry times (exec / console): 542 / 537 ms [DEBUG] All HSPHY ports disabled, skipping HSPHY loading [INFO ] Disabling PCH PCIE ClockGating+PowerGating. [INFO ] PCI 1.0, PIN A, using IRQ #16 ... [DEBUG] BS: BS_DEV_ENABLE exit times (exec / console): 21 / 4 ms [INFO ] Initializing devices... [DEBUG] PCI: 00:00:00.0 init [INFO ] CPU TDP = 28 Watts [INFO ] CPU PL1 = 28 Watts [INFO ] CPU PL2 = 28 Watts [INFO ] CPU PL4 = 64 Watts [DEBUG] PCI: 00:00:00.0 init finished in 14 msecs Change-Id: I9d6f32f2f3fbf73e46a25d77e4dba7711ed70d5f Signed-off-by: Kilian Krause Reviewed-on: https://review.coreboot.org/c/coreboot/+/88957 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Matt DeVillier --- src/soc/intel/alderlake/chip.h | 1 + src/soc/intel/alderlake/vr_config.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index db8965e40e..8e143f0f65 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -198,6 +198,7 @@ static const struct { { PCI_DID_INTEL_RPL_P_ID_6, RPL_P_682_642_482_45W_CORE, TDP_45W }, { PCI_DID_INTEL_RPL_P_ID_7, RPL_P_682_642_482_45W_CORE, TDP_45W }, { PCI_DID_INTEL_RPL_P_ID_8, RPL_P_682_642_482_45W_CORE, TDP_45W }, + { PCI_DID_INTEL_RPL_P_ID_8, RPL_P_682_482_282_28W_CORE, TDP_28W }, { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_35W_CORE, TDP_35W }, { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_65W_CORE, TDP_65W }, { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_95W_CORE, TDP_95W }, diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index 6a29a02960..06fddc864b 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -159,6 +159,7 @@ static const struct vr_lookup vr_config_ll[] = { { PCI_DID_INTEL_RPL_P_ID_6, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_7, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_8, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, + { PCI_DID_INTEL_RPL_P_ID_8, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, @@ -231,6 +232,7 @@ static const struct vr_lookup vr_config_icc[] = { { PCI_DID_INTEL_RPL_P_ID_6, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, { PCI_DID_INTEL_RPL_P_ID_7, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, { PCI_DID_INTEL_RPL_P_ID_8, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, + { PCI_DID_INTEL_RPL_P_ID_8, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) }, { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_ICC(280, 30) }, { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_ICC(280, 30) }, { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_ICC(240, 30) }, @@ -303,6 +305,7 @@ static const struct vr_lookup vr_config_tdc_timewindow[] = { { PCI_DID_INTEL_RPL_P_ID_6, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_7, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_8, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_RPL_P_ID_8, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, @@ -375,6 +378,7 @@ static const struct vr_lookup vr_config_tdc_currentlimit[] = { { PCI_DID_INTEL_RPL_P_ID_6, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, { PCI_DID_INTEL_RPL_P_ID_7, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, { PCI_DID_INTEL_RPL_P_ID_8, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, + { PCI_DID_INTEL_RPL_P_ID_8, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(33, 33) }, { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 22) }, { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 22) }, { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) },