vc/intel/fsp: Update PTL FSP headers from 2382_01 to 2431.00
Update generated FSP headers for Panther Lake from 2431.00 Changes include: - Update in FspmUpd.h : Adjusted offsets and updated comments. - FspsUpd.h: added ThcInterruptPinMuxing, ThcMode and ThcWakeOnTouch UPDs - MemInfoHob.h : Updated comments BUG=b:378789201 TEST=Able to build google/fatcat Change-Id: I1c1fed8f7ba9d25fdce5bbac3a9687800db33613 Signed-off-by: alokagar <alok.agarwal@intel.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: <srinivas.kulkarni@intel.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
This commit is contained in:
Subrata Banik
parent
a417acdfbc
commit
c107755701
3 changed files with 234 additions and 219 deletions
|
|
@ -802,8 +802,9 @@ typedef struct {
|
|||
**/
|
||||
UINT8 Reserved22;
|
||||
|
||||
/** Offset 0x024A - PPR Repair BankGroup
|
||||
PPR repair BankGroup: User chooses to force repair specifc address
|
||||
/** Offset 0x024A - tCCD_L_WR
|
||||
Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same
|
||||
bank groups
|
||||
**/
|
||||
UINT16 tCCD_L_WR;
|
||||
|
||||
|
|
@ -841,8 +842,8 @@ typedef struct {
|
|||
**/
|
||||
UINT8 Reserved23[12];
|
||||
|
||||
/** Offset 0x026C - DCC Phase Clk Calibration
|
||||
Enable/disable DCC Phase Clk Calibration
|
||||
/** Offset 0x026C - RDDQODTT
|
||||
Enable/disable Read DQ ODT Training
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT32 RDDQODTT;
|
||||
|
|
@ -853,8 +854,8 @@ typedef struct {
|
|||
**/
|
||||
UINT32 RDCTLET;
|
||||
|
||||
/** Offset 0x0274 - EMPHASIS
|
||||
Enable/disable DCC Tline Clk Calibration
|
||||
/** Offset 0x0274 - RxVref Pre EMPHASIS Training
|
||||
Enable/Disable Pre EMPHASIS Training
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 EMPHASIS;
|
||||
|
|
@ -983,8 +984,8 @@ typedef struct {
|
|||
**/
|
||||
UINT8 ERDTC2D;
|
||||
|
||||
/** Offset 0x028F - Early Read Time Centering 2D
|
||||
Enables/Disable Early Read Time Centering 2D
|
||||
/** Offset 0x028F - Unmatched Write Time Centering 1D
|
||||
Enable/Disable Unmatched Write Time Centering 1D
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 UNMATCHEDWRTC1D;
|
||||
|
|
@ -1478,8 +1479,8 @@ typedef struct {
|
|||
**/
|
||||
UINT8 Reserved41;
|
||||
|
||||
/** Offset 0x033C - VccClk Voltage Override
|
||||
# is multiple of 1mV where 0 means Auto.
|
||||
/** Offset 0x033C - Margin limit check L2
|
||||
Margin limit check L2 threshold: <b>100=Default</b>
|
||||
**/
|
||||
UINT16 MarginLimitL2;
|
||||
|
||||
|
|
@ -1736,21 +1737,21 @@ typedef struct {
|
|||
|
||||
/** Offset 0x05BF - Reserved
|
||||
**/
|
||||
UINT8 Reserved50[5];
|
||||
UINT8 Reserved50[6];
|
||||
|
||||
/** Offset 0x05C4 - Usage type for ClkSrc
|
||||
/** Offset 0x05C5 - Usage type for ClkSrc
|
||||
0-23: PCH rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used
|
||||
**/
|
||||
UINT8 PcieClkSrcUsage[18];
|
||||
|
||||
/** Offset 0x05D6 - ClkReq-to-ClkSrc mapping
|
||||
/** Offset 0x05D7 - ClkReq-to-ClkSrc mapping
|
||||
Number of ClkReq signal assigned to ClkSrc
|
||||
**/
|
||||
UINT8 PcieClkSrcClkReq[18];
|
||||
|
||||
/** Offset 0x05E8 - Reserved
|
||||
/** Offset 0x05E9 - Reserved
|
||||
**/
|
||||
UINT8 Reserved51[48];
|
||||
UINT8 Reserved51[47];
|
||||
|
||||
/** Offset 0x0618 - Enable PCIE RP Mask
|
||||
Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
|
||||
|
|
@ -1769,7 +1770,7 @@ typedef struct {
|
|||
UINT8 Reserved52[3];
|
||||
|
||||
/** Offset 0x0620 - Serial Io Uart Debug Mmio Base
|
||||
Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
|
||||
Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdLpssUartMode
|
||||
= SerialIoUartPci.
|
||||
**/
|
||||
UINT32 SerialIoUartDebugMmioBase;
|
||||
|
|
@ -1823,8 +1824,8 @@ typedef struct {
|
|||
**/
|
||||
UINT8 SerialIoUartDebugDataBits;
|
||||
|
||||
/** Offset 0x062E - Enable/Disable SA IPU
|
||||
Enable(Default): Enable SA IPU, Disable: Disable SA IPU
|
||||
/** Offset 0x062E - IMGU CLKOUT Configuration
|
||||
The configuration of IMGU CLKOUT, 0: Disable;<b>1: Enable</b>.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 ImguClkOutEn[6];
|
||||
|
|
@ -2192,303 +2193,302 @@ typedef struct {
|
|||
**/
|
||||
UINT8 BistOnReset;
|
||||
|
||||
/** Offset 0x07D7 - Enable or Disable VMX
|
||||
/** Offset 0x07D7 - Reserved
|
||||
**/
|
||||
UINT8 Reserved70;
|
||||
|
||||
/** Offset 0x07D8 - Enable or Disable VMX
|
||||
Enable or Disable VMX, When enabled, a VMM can utilize the additional hardware capabilities
|
||||
provided by Vanderpool Technology. 0: Disable; <b>1: Enable</b>.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 VmxEnable;
|
||||
|
||||
/** Offset 0x07D8 - Processor Early Power On Configuration FCLK setting
|
||||
/** Offset 0x07D9 - Processor Early Power On Configuration FCLK setting
|
||||
FCLK frequency can take values of 400MHz, 800MHz and 1GHz. <b>0: 800 MHz (ULT/ULX)</b>.
|
||||
<b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved
|
||||
0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved
|
||||
**/
|
||||
UINT8 FClkFrequency;
|
||||
|
||||
/** Offset 0x07D9 - Enable CPU CrashLog
|
||||
/** Offset 0x07DA - Enable CPU CrashLog
|
||||
Enable or Disable CPU CrashLog; 0: Disable; <b>1: Enable</b>.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 CpuCrashLogEnable;
|
||||
|
||||
/** Offset 0x07DA - Enable or Disable TME
|
||||
/** Offset 0x07DB - Enable or Disable TME
|
||||
Configure Total Memory Encryption (TME) to protect DRAM data from physical attacks.
|
||||
<b>0: Disable</b>; 1: Enable.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 TmeEnable;
|
||||
|
||||
/** Offset 0x07DB - CPU Run Control
|
||||
/** Offset 0x07DC - CPU Run Control
|
||||
Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; <b>2:
|
||||
No Change</b>
|
||||
0:Disabled, 1:Enabled, 2:No Change
|
||||
**/
|
||||
UINT8 DebugInterfaceEnable;
|
||||
|
||||
/** Offset 0x07DC - CPU Run Control Lock
|
||||
/** Offset 0x07DD - CPU Run Control Lock
|
||||
Lock or Unlock CPU Run Control; 0: Disable; <b>1: Enable</b>.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 DebugInterfaceLockEnable;
|
||||
|
||||
/** Offset 0x07DD - Enable CPU CrashLog GPRs dump
|
||||
/** Offset 0x07DE - Enable CPU CrashLog GPRs dump
|
||||
Enable or Disable CPU CrashLog GPRs dump; <b>0: Disable</b>; 1: Enable; 2: Only
|
||||
disable Smm GPRs dump
|
||||
0:Disabled, 1:Enabled, 2:Only Smm GPRs Disabled
|
||||
**/
|
||||
UINT8 CrashLogGprs;
|
||||
|
||||
/** Offset 0x07DE - Over clocking Lock
|
||||
/** Offset 0x07DF - Over clocking Lock
|
||||
Lock Overclocking. 0: Disable; <b>1: Enable</b>
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 OcLock;
|
||||
|
||||
/** Offset 0x07DF - CPU ratio value
|
||||
/** Offset 0x07E0 - CPU ratio value
|
||||
This value must be between Max Efficiency Ratio (LFM) and Maximum non-turbo ratio
|
||||
set by Hardware (HFM). Valid Range 0 to 63.
|
||||
**/
|
||||
UINT8 CpuRatio;
|
||||
|
||||
/** Offset 0x07E0 - Number of active big cores
|
||||
/** Offset 0x07E1 - Number of active big cores
|
||||
Number of P-cores to enable in each processor package. Note: Number of P-Cores and
|
||||
E-Cores are looked at together. When both are {0,0
|
||||
0:Disable all big cores, 1:1, 2:2, 3:3, 0xFF:Active all big cores
|
||||
**/
|
||||
UINT8 ActiveCoreCount;
|
||||
|
||||
/** Offset 0x07E1 - Reserved
|
||||
/** Offset 0x07E2 - Reserved
|
||||
**/
|
||||
UINT8 Reserved70[3];
|
||||
UINT8 Reserved71[6];
|
||||
|
||||
/** Offset 0x07E4 - PrmrrSize
|
||||
/** Offset 0x07E8 - PrmrrSize
|
||||
Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
|
||||
**/
|
||||
UINT32 PrmrrSize;
|
||||
|
||||
/** Offset 0x07E8 - Tseg Size
|
||||
/** Offset 0x07EC - Tseg Size
|
||||
Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
|
||||
0x0400000:4MB, 0x01000000:16MB
|
||||
**/
|
||||
UINT32 TsegSize;
|
||||
|
||||
/** Offset 0x07EC - SmmRelocationEnable Enable
|
||||
/** Offset 0x07F0 - SmmRelocationEnable Enable
|
||||
Enable or Disable SmmRelocationEnable. <b>0: Disable</b>, 1:Enable
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 SmmRelocationEnable;
|
||||
|
||||
/** Offset 0x07ED - TCC Activation Offset
|
||||
/** Offset 0x07F1 - TCC Activation Offset
|
||||
TCC Activation Offset. Offset from factory set TCC activation temperature at which
|
||||
the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
|
||||
Temperature, in volts. <b>Default = 0h</b>.
|
||||
**/
|
||||
UINT8 TccActivationOffset;
|
||||
|
||||
/** Offset 0x07EE - Reserved
|
||||
/** Offset 0x07F2 - Reserved
|
||||
**/
|
||||
UINT8 Reserved71[90];
|
||||
UINT8 Reserved72[98];
|
||||
|
||||
/** Offset 0x0848 - SinitMemorySize
|
||||
/** Offset 0x0854 - SinitMemorySize
|
||||
Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
|
||||
**/
|
||||
UINT32 SinitMemorySize;
|
||||
|
||||
/** Offset 0x084C - Reserved
|
||||
**/
|
||||
UINT8 Reserved72[4];
|
||||
|
||||
/** Offset 0x0850 - TxtDprMemoryBase
|
||||
/** Offset 0x0858 - TxtDprMemoryBase
|
||||
Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable
|
||||
**/
|
||||
UINT64 TxtDprMemoryBase;
|
||||
|
||||
/** Offset 0x0858 - TxtHeapMemorySize
|
||||
/** Offset 0x0860 - TxtHeapMemorySize
|
||||
Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
|
||||
**/
|
||||
UINT32 TxtHeapMemorySize;
|
||||
|
||||
/** Offset 0x085C - TxtDprMemorySize
|
||||
/** Offset 0x0864 - TxtDprMemorySize
|
||||
Reserve DPR memory size (0-255) MB. 0: Disable, define default value of TxtDprMemorySize
|
||||
, 1: enable
|
||||
**/
|
||||
UINT32 TxtDprMemorySize;
|
||||
|
||||
/** Offset 0x0860 - TxtLcpPdBase
|
||||
/** Offset 0x0868 - TxtLcpPdBase
|
||||
Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable
|
||||
**/
|
||||
UINT64 TxtLcpPdBase;
|
||||
|
||||
/** Offset 0x0868 - TxtLcpPdSize
|
||||
/** Offset 0x0870 - TxtLcpPdSize
|
||||
Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable
|
||||
**/
|
||||
UINT64 TxtLcpPdSize;
|
||||
|
||||
/** Offset 0x0870 - BiosAcmBase
|
||||
/** Offset 0x0878 - BiosAcmBase
|
||||
Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
|
||||
**/
|
||||
UINT64 BiosAcmBase;
|
||||
|
||||
/** Offset 0x0878 - BiosAcmSize
|
||||
/** Offset 0x0880 - BiosAcmSize
|
||||
Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable
|
||||
**/
|
||||
UINT32 BiosAcmSize;
|
||||
|
||||
/** Offset 0x087C - ApStartupBase
|
||||
/** Offset 0x0884 - ApStartupBase
|
||||
Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
|
||||
**/
|
||||
UINT32 ApStartupBase;
|
||||
|
||||
/** Offset 0x0880 - TgaSize
|
||||
/** Offset 0x0888 - TgaSize
|
||||
Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable
|
||||
**/
|
||||
UINT32 TgaSize;
|
||||
|
||||
/** Offset 0x0884 - IsTPMPresence
|
||||
/** Offset 0x088C - IsTPMPresence
|
||||
IsTPMPresence default values
|
||||
**/
|
||||
UINT8 IsTPMPresence;
|
||||
|
||||
/** Offset 0x0885 - Reserved
|
||||
/** Offset 0x088D - Reserved
|
||||
**/
|
||||
UINT8 Reserved73[157];
|
||||
|
||||
/** Offset 0x0922 - Thermal Design Current enable/disable
|
||||
/** Offset 0x092A - Thermal Design Current enable/disable
|
||||
Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable. [0] for IA,
|
||||
[1] for GT, [2] for SA, [3] through [5] are Reserved.
|
||||
[1] for GT, [2] for SA, [3] for atom, [4]-[5] are Reserved.
|
||||
**/
|
||||
UINT8 TdcEnable[6];
|
||||
|
||||
/** Offset 0x0928 - Reserved
|
||||
/** Offset 0x0930 - Reserved
|
||||
**/
|
||||
UINT8 Reserved74[24];
|
||||
|
||||
/** Offset 0x0940 - Thermal Design Current time window
|
||||
PSYS Offset defined in 1/1000 increments. <b>0 - Auto</b> This is an 32-bit signed
|
||||
value (2's complement). Units 1/1000, Range is [-128000, 127999]. For an offset
|
||||
of 25.348, enter 25348.
|
||||
/** Offset 0x0948 - Thermal Design Current time window
|
||||
Auto = 0 is default. Range is from 1ms to 448s. <b>0: Auto</b>. [0] for IA, [1]
|
||||
for GT, [2] for SA, [3] for atom, [4]-[5] are Reserved.
|
||||
**/
|
||||
UINT8 TdcTimeWindow[24];
|
||||
UINT32 TdcTimeWindow[6];
|
||||
|
||||
/** Offset 0x0958 - Reserved
|
||||
/** Offset 0x0960 - Reserved
|
||||
**/
|
||||
UINT8 Reserved75[8];
|
||||
|
||||
/** Offset 0x0960 - DLVR RFI Enable
|
||||
/** Offset 0x0968 - DLVR RFI Enable
|
||||
Enable/Disable DLVR RFI frequency hopping. 0: Disable; <b>1: Enable</b>.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 DlvrRfiEnable;
|
||||
|
||||
/** Offset 0x0961 - Reserved
|
||||
/** Offset 0x0969 - Reserved
|
||||
**/
|
||||
UINT8 Reserved76[25];
|
||||
|
||||
/** Offset 0x097A - Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled.
|
||||
/** Offset 0x0982 - Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled.
|
||||
Enable/Disable VR FastVmode; <b>0: Disable</b>; 1: Enable.For all VR by domain
|
||||
0: Disable, 1: Enable
|
||||
**/
|
||||
UINT8 EnableFastVmode[6];
|
||||
|
||||
/** Offset 0x0980 - Reserved
|
||||
/** Offset 0x0988 - Reserved
|
||||
**/
|
||||
UINT8 Reserved77[26];
|
||||
|
||||
/** Offset 0x099A - PCH Port80 Route
|
||||
/** Offset 0x09A2 - PCH Port80 Route
|
||||
Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PchPort80Route;
|
||||
|
||||
/** Offset 0x099B - GPIO Override
|
||||
/** Offset 0x09A3 - GPIO Override
|
||||
Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings
|
||||
before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO
|
||||
configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use
|
||||
**/
|
||||
UINT8 GpioOverride;
|
||||
|
||||
/** Offset 0x099C - Reserved
|
||||
/** Offset 0x09A4 - Reserved
|
||||
**/
|
||||
UINT8 Reserved78[4];
|
||||
|
||||
/** Offset 0x09A0 - PMR Size
|
||||
/** Offset 0x09A8 - PMR Size
|
||||
Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
|
||||
**/
|
||||
UINT32 DmaBufferSize;
|
||||
|
||||
/** Offset 0x09A4 - The policy for VTd driver behavior
|
||||
/** Offset 0x09AC - The policy for VTd driver behavior
|
||||
BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS
|
||||
**/
|
||||
UINT8 PreBootDmaMask;
|
||||
|
||||
/** Offset 0x09A5 - State of DMA_CONTROL_GUARANTEE bit in the DMAR table
|
||||
/** Offset 0x09AD - State of DMA_CONTROL_GUARANTEE bit in the DMAR table
|
||||
0=Disable/Clear, 1=Enable/Set
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 DmaControlGuarantee;
|
||||
|
||||
/** Offset 0x09A6 - Disable VT-d
|
||||
/** Offset 0x09AE - Disable VT-d
|
||||
0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 VtdDisable;
|
||||
|
||||
/** Offset 0x09A7 - Reserved
|
||||
/** Offset 0x09AF - Reserved
|
||||
**/
|
||||
UINT8 Reserved79;
|
||||
|
||||
/** Offset 0x09A8 - Base addresses for VT-d function MMIO access
|
||||
/** Offset 0x09B0 - Base addresses for VT-d function MMIO access
|
||||
Base addresses for VT-d MMIO access per VT-d engine
|
||||
**/
|
||||
UINT32 VtdBaseAddress[9];
|
||||
|
||||
/** Offset 0x09CC - Reserved
|
||||
/** Offset 0x09D4 - Reserved
|
||||
**/
|
||||
UINT8 Reserved80[20];
|
||||
|
||||
/** Offset 0x09E0 - MMIO Size
|
||||
/** Offset 0x09E8 - MMIO Size
|
||||
Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
|
||||
**/
|
||||
UINT16 MmioSize;
|
||||
|
||||
/** Offset 0x09E2 - MMIO size adjustment for AUTO mode
|
||||
/** Offset 0x09EA - MMIO size adjustment for AUTO mode
|
||||
Positive number means increasing MMIO size, Negative value means decreasing MMIO
|
||||
size: 0 (Default)=no change to AUTO mode MMIO size
|
||||
**/
|
||||
UINT16 MmioSizeAdjustment;
|
||||
|
||||
/** Offset 0x09E4 - Reserved
|
||||
/** Offset 0x09EC - Reserved
|
||||
**/
|
||||
UINT8 Reserved81[36];
|
||||
|
||||
/** Offset 0x0A08 - Enable above 4GB MMIO resource support
|
||||
/** Offset 0x0A10 - Enable above 4GB MMIO resource support
|
||||
Enable/disable above 4GB MMIO resource support
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 EnableAbove4GBMmio;
|
||||
|
||||
/** Offset 0x0A09 - Enable/Disable SA CRID
|
||||
/** Offset 0x0A11 - Enable/Disable SA CRID
|
||||
Enable: SA CRID, Disable (Default): SA CRID
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 CridEnable;
|
||||
|
||||
/** Offset 0x0A0A - Reserved
|
||||
/** Offset 0x0A12 - Reserved
|
||||
**/
|
||||
UINT8 Reserved82[34];
|
||||
UINT8 Reserved82[10];
|
||||
|
||||
/** Offset 0x0A2C - Enable/Disable CrashLog Device
|
||||
/** Offset 0x0A1C - Enable/Disable CrashLog Device
|
||||
Enable or Disable CrashLog/Telemetry Device 0- Disable, <b>1- Enable</b>
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT32 CpuCrashLogDevice;
|
||||
|
||||
/** Offset 0x0A30 - Reserved
|
||||
/** Offset 0x0A20 - Reserved
|
||||
**/
|
||||
UINT8 Reserved83[17];
|
||||
UINT8 Reserved83[20];
|
||||
|
||||
/** Offset 0x0A41 - Platform Debug Option
|
||||
/** Offset 0x0A34 - Platform Debug Option
|
||||
Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n
|
||||
\n
|
||||
Enabled Trace ready: TraceHub is enabled and allowed S0ix.\n
|
||||
|
|
@ -2501,122 +2501,122 @@ typedef struct {
|
|||
**/
|
||||
UINT8 PlatformDebugOption;
|
||||
|
||||
/** Offset 0x0A42 - Reserved
|
||||
/** Offset 0x0A35 - Reserved
|
||||
**/
|
||||
UINT8 Reserved84[14];
|
||||
|
||||
/** Offset 0x0A50 - Program GPIOs for LFP on DDI port-A device
|
||||
/** Offset 0x0A43 - Program GPIOs for LFP on DDI port-A device
|
||||
0=Disabled,1(Default)=eDP, 2=MIPI DSI
|
||||
0:Disabled, 1:eDP, 2:MIPI DSI
|
||||
**/
|
||||
UINT8 DdiPortAConfig;
|
||||
|
||||
/** Offset 0x0A51 - Reserved
|
||||
/** Offset 0x0A44 - Reserved
|
||||
**/
|
||||
UINT8 Reserved85[3];
|
||||
UINT8 Reserved85[2];
|
||||
|
||||
/** Offset 0x0A54 - Program GPIOs for LFP on DDI port-B device
|
||||
/** Offset 0x0A46 - Program GPIOs for LFP on DDI port-B device
|
||||
0(Default)=Disabled,1=eDP, 2=MIPI DSI
|
||||
0:Disabled, 1:eDP, 2:MIPI DSI
|
||||
**/
|
||||
UINT8 DdiPortBConfig;
|
||||
|
||||
/** Offset 0x0A55 - Enable or disable HPD of DDI port A
|
||||
/** Offset 0x0A47 - Enable or disable HPD of DDI port A
|
||||
0(Default)=Disable, 1=Enable
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 DdiPortAHpd;
|
||||
|
||||
/** Offset 0x0A56 - Enable or disable HPD of DDI port B
|
||||
/** Offset 0x0A48 - Enable or disable HPD of DDI port B
|
||||
0=Disable, 1(Default)=Enable
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 DdiPortBHpd;
|
||||
|
||||
/** Offset 0x0A57 - Enable or disable HPD of DDI port C
|
||||
/** Offset 0x0A49 - Enable or disable HPD of DDI port C
|
||||
0(Default)=Disable, 1=Enable
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 DdiPortCHpd;
|
||||
|
||||
/** Offset 0x0A58 - Enable or disable HPD of DDI port 1
|
||||
/** Offset 0x0A4A - Enable or disable HPD of DDI port 1
|
||||
0=Disable, 1(Default)=Enable
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 DdiPort1Hpd;
|
||||
|
||||
/** Offset 0x0A59 - Enable or disable HPD of DDI port 2
|
||||
/** Offset 0x0A4B - Enable or disable HPD of DDI port 2
|
||||
0(Default)=Disable, 1=Enable
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 DdiPort2Hpd;
|
||||
|
||||
/** Offset 0x0A5A - Enable or disable HPD of DDI port 3
|
||||
/** Offset 0x0A4C - Enable or disable HPD of DDI port 3
|
||||
0(Default)=Disable, 1=Enable
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 DdiPort3Hpd;
|
||||
|
||||
/** Offset 0x0A5B - Enable or disable HPD of DDI port 4
|
||||
/** Offset 0x0A4D - Enable or disable HPD of DDI port 4
|
||||
0(Default)=Disable, 1=Enable
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 DdiPort4Hpd;
|
||||
|
||||
/** Offset 0x0A5C - Enable or disable DDC of DDI port A
|
||||
/** Offset 0x0A4E - Enable or disable DDC of DDI port A
|
||||
0(Default)=Disable, 1=Enable
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 DdiPortADdc;
|
||||
|
||||
/** Offset 0x0A5D - Enable or disable DDC of DDI port B
|
||||
/** Offset 0x0A4F - Enable or disable DDC of DDI port B
|
||||
0=Disable, 1(Default)=Enable
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 DdiPortBDdc;
|
||||
|
||||
/** Offset 0x0A5E - Enable or disable DDC of DDI port C
|
||||
/** Offset 0x0A50 - Enable or disable DDC of DDI port C
|
||||
0(Default)=Disable, 1=Enable
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 DdiPortCDdc;
|
||||
|
||||
/** Offset 0x0A5F - Enable DDC setting of DDI Port 1
|
||||
/** Offset 0x0A51 - Enable DDC setting of DDI Port 1
|
||||
0(Default)=Disable, 1=Enable
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 DdiPort1Ddc;
|
||||
|
||||
/** Offset 0x0A60 - Enable DDC setting of DDI Port 2
|
||||
/** Offset 0x0A52 - Enable DDC setting of DDI Port 2
|
||||
0(Default)=Disable, 1=Enable
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 DdiPort2Ddc;
|
||||
|
||||
/** Offset 0x0A61 - Enable DDC setting of DDI Port 3
|
||||
/** Offset 0x0A53 - Enable DDC setting of DDI Port 3
|
||||
0(Default)=Disable, 1=Enable
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 DdiPort3Ddc;
|
||||
|
||||
/** Offset 0x0A62 - Enable DDC setting of DDI Port 4
|
||||
/** Offset 0x0A54 - Enable DDC setting of DDI Port 4
|
||||
0(Default)=Disable, 1=Enable
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 DdiPort4Ddc;
|
||||
|
||||
/** Offset 0x0A63 - Reserved
|
||||
/** Offset 0x0A55 - Reserved
|
||||
**/
|
||||
UINT8 Reserved86[5];
|
||||
UINT8 Reserved86[3];
|
||||
|
||||
/** Offset 0x0A68 - Temporary MMIO address for GMADR
|
||||
/** Offset 0x0A58 - Temporary MMIO address for GMADR
|
||||
The reference code will use this as Temporary MMIO address space to access GMADR
|
||||
Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to
|
||||
(GmAdr + 256MB). Default is (PciExpressBaseAddress - 256MB) to (PciExpressBaseAddress - 0x1)
|
||||
**/
|
||||
UINT64 LMemBar;
|
||||
|
||||
/** Offset 0x0A70 - Temporary MMIO address for GTTMMADR
|
||||
/** Offset 0x0A60 - Temporary MMIO address for GTTMMADR
|
||||
The reference code will use this as Temporary MMIO address space to access GTTMMADR
|
||||
Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr
|
||||
to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO
|
||||
|
|
@ -2624,104 +2624,104 @@ typedef struct {
|
|||
**/
|
||||
UINT64 GttMmAdr;
|
||||
|
||||
/** Offset 0x0A78 - Reserved
|
||||
/** Offset 0x0A68 - Reserved
|
||||
**/
|
||||
UINT8 Reserved87[2];
|
||||
|
||||
/** Offset 0x0A7A - Enable/Disable Memory Bandwidth Compression
|
||||
/** Offset 0x0A6A - Enable/Disable Memory Bandwidth Compression
|
||||
0=Disable, 1(Default)=Enable
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 MemoryBandwidthCompression;
|
||||
|
||||
/** Offset 0x0A7B - Panel Power Enable
|
||||
/** Offset 0x0A6B - Panel Power Enable
|
||||
Control for enabling/disabling VDD force bit (Required only for early enabling of
|
||||
eDP panel). 0=Disable, 1(Default)=Enable
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PanelPowerEnable;
|
||||
|
||||
/** Offset 0x0A7C - Selection of the primary display device
|
||||
/** Offset 0x0A6C - Selection of the primary display device
|
||||
3(Default)=AUTO, 0=IGFX, 4=Hybrid Graphics
|
||||
3:AUTO, 0:IGFX, 4:HG
|
||||
**/
|
||||
UINT8 PrimaryDisplay;
|
||||
|
||||
/** Offset 0x0A7D - TCSS USB HOST (xHCI) Enable
|
||||
/** Offset 0x0A6D - TCSS USB HOST (xHCI) Enable
|
||||
Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 TcssXhciEn;
|
||||
|
||||
/** Offset 0x0A7E - Reserved
|
||||
/** Offset 0x0A6E - Reserved
|
||||
**/
|
||||
UINT8 Reserved88[4];
|
||||
|
||||
/** Offset 0x0A82 - TCSS Type C Port 0
|
||||
/** Offset 0x0A72 - TCSS Type C Port 0
|
||||
Set TCSS Type C Port 0 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
|
||||
7=FULL_FUN
|
||||
0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN
|
||||
**/
|
||||
UINT8 TcssPort0;
|
||||
|
||||
/** Offset 0x0A83 - TCSS Type C Port 1
|
||||
/** Offset 0x0A73 - TCSS Type C Port 1
|
||||
Set TCSS Type C Port 1 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
|
||||
7=FULL_FUN
|
||||
0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN
|
||||
**/
|
||||
UINT8 TcssPort1;
|
||||
|
||||
/** Offset 0x0A84 - TCSS Type C Port 2
|
||||
/** Offset 0x0A74 - TCSS Type C Port 2
|
||||
Set TCSS Type C Port 2 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
|
||||
7=FULL_FUN
|
||||
0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN
|
||||
**/
|
||||
UINT8 TcssPort2;
|
||||
|
||||
/** Offset 0x0A85 - TCSS Type C Port 3
|
||||
/** Offset 0x0A75 - TCSS Type C Port 3
|
||||
Set TCSS Type C Port 3 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
|
||||
7=FULL_FUN
|
||||
0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN
|
||||
**/
|
||||
UINT8 TcssPort3;
|
||||
|
||||
/** Offset 0x0A86 - Reserved
|
||||
/** Offset 0x0A76 - Reserved
|
||||
**/
|
||||
UINT8 Reserved89[2];
|
||||
|
||||
/** Offset 0x0A88 - TypeC port GPIO setting
|
||||
/** Offset 0x0A78 - TypeC port GPIO setting
|
||||
GPIO Pin number for Type C Aux orientation setting, use the GpioPad that is defined
|
||||
in GpioPinsXXX.h as argument.(XXX is platform name, Ex: Ptl = PantherLake)
|
||||
**/
|
||||
UINT32 IomTypeCPortPadCfg[12];
|
||||
|
||||
/** Offset 0x0AB8 - TCSS Aux Orientation Override Enable
|
||||
/** Offset 0x0AA8 - TCSS Aux Orientation Override Enable
|
||||
Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
|
||||
**/
|
||||
UINT16 TcssAuxOri;
|
||||
|
||||
/** Offset 0x0ABA - TCSS HSL Orientation Override Enable
|
||||
/** Offset 0x0AAA - TCSS HSL Orientation Override Enable
|
||||
Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
|
||||
**/
|
||||
UINT16 TcssHslOri;
|
||||
|
||||
/** Offset 0x0ABC - CNVi DDR RFI Mitigation
|
||||
/** Offset 0x0AAC - CNVi DDR RFI Mitigation
|
||||
Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 CnviDdrRfim;
|
||||
|
||||
/** Offset 0x0ABD - SOC Trace Hub Mode
|
||||
/** Offset 0x0AAD - SOC Trace Hub Mode
|
||||
Enable/Disable SOC TraceHub
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 SocTraceHubMode;
|
||||
|
||||
/** Offset 0x0ABE - Reserved
|
||||
/** Offset 0x0AAE - Reserved
|
||||
**/
|
||||
UINT8 Reserved90[4];
|
||||
|
||||
/** Offset 0x0AC2 - Internal Graphics Pre-allocated Memory
|
||||
/** Offset 0x0AB2 - Internal Graphics Pre-allocated Memory
|
||||
Size of memory preallocated for internal graphics.
|
||||
0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB,
|
||||
0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB,
|
||||
|
|
@ -2729,174 +2729,175 @@ typedef struct {
|
|||
**/
|
||||
UINT16 IgdDvmt50PreAlloc;
|
||||
|
||||
/** Offset 0x0AC4 - Internal Graphics
|
||||
/** Offset 0x0AB4 - Internal Graphics
|
||||
Enable/disable internal graphics.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 InternalGraphics;
|
||||
|
||||
/** Offset 0x0AC5 - Reserved
|
||||
/** Offset 0x0AB5 - Reserved
|
||||
**/
|
||||
UINT8 Reserved91[7];
|
||||
|
||||
/** Offset 0x0ACC - Fore Single Rank config
|
||||
Enables/Disable Fore Single Rank config
|
||||
/** Offset 0x0ABC - DynamicMemoryBoost
|
||||
Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is
|
||||
an XMP Profile; otherwise ignored. <b>0=Disabled</b>, 1=Enabled.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT32 DynamicMemoryBoost;
|
||||
|
||||
/** Offset 0x0AD0 - Fore Single Rank config
|
||||
Enables/Disable Fore Single Rank config
|
||||
/** Offset 0x0AC0 - RealtimeMemoryFrequency
|
||||
Enable/Disable Realtime Memory Frequency feature. Only valid if SpdProfileSelected
|
||||
is an XMP Profile; otherwise ignored. <b>0=Disabled</b>, 1=Enabled.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT32 RealtimeMemoryFrequency;
|
||||
|
||||
/** Offset 0x0AD4 - Reserved
|
||||
/** Offset 0x0AC4 - Reserved
|
||||
**/
|
||||
UINT8 Reserved92[9];
|
||||
|
||||
/** Offset 0x0ADD - Vref Offset
|
||||
/** Offset 0x0ACD - Vref Offset
|
||||
Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset
|
||||
0xFA:-6, 0xFB:-5, 0xFC:-4, 0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3, 4:+4,
|
||||
5:+5, 6:+6
|
||||
**/
|
||||
UINT8 VrefOffset;
|
||||
|
||||
/** Offset 0x0ADE - Reserved
|
||||
/** Offset 0x0ACE - Reserved
|
||||
**/
|
||||
UINT8 Reserved93[2];
|
||||
|
||||
/** Offset 0x0AE0 - tRRSG Delta
|
||||
/** Offset 0x0AD0 - tRRSG Delta
|
||||
Delay between Read-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT
|
||||
delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
|
||||
of [-127..127]
|
||||
**/
|
||||
UINT8 tRRSG;
|
||||
|
||||
/** Offset 0x0AE1 - tRRDG Delta
|
||||
/** Offset 0x0AD1 - tRRDG Delta
|
||||
Delay between Read-to-Read commands in different Bank Group. 0 - Auto. Signed TAT
|
||||
delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
|
||||
of [-127..127]
|
||||
**/
|
||||
UINT8 tRRDG;
|
||||
|
||||
/** Offset 0x0AE2 - tRRDR Delta
|
||||
/** Offset 0x0AD2 - tRRDR Delta
|
||||
Delay between Read-to-Read commands in different Ranks. 0 - Auto. Signed TAT delta
|
||||
is (Value - 128). Input value range of [1..255] will give a TAT delta range of
|
||||
[-127..127]
|
||||
**/
|
||||
UINT8 tRRDR;
|
||||
|
||||
/** Offset 0x0AE3 - tRRDD Delta
|
||||
/** Offset 0x0AD3 - tRRDD Delta
|
||||
Delay between Read-to-Read commands in different DIMMs. 0 - Auto. Signed TAT delta
|
||||
is (Value - 128). Input value range of [1..255] will give a TAT delta range of
|
||||
[-127..127]
|
||||
**/
|
||||
UINT8 tRRDD;
|
||||
|
||||
/** Offset 0x0AE4 - tWRSG Delta
|
||||
/** Offset 0x0AD4 - tWRSG Delta
|
||||
Delay between Write-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT
|
||||
delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
|
||||
of [-127..127]
|
||||
**/
|
||||
UINT8 tWRSG;
|
||||
|
||||
/** Offset 0x0AE5 - tWRDG Delta
|
||||
/** Offset 0x0AD5 - tWRDG Delta
|
||||
Delay between Write-to-Read commands in different Bank Group. 0 - Auto. Signed TAT
|
||||
delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
|
||||
of [-127..127]
|
||||
**/
|
||||
UINT8 tWRDG;
|
||||
|
||||
/** Offset 0x0AE6 - tWRDR Delta
|
||||
/** Offset 0x0AD6 - tWRDR Delta
|
||||
Delay between Write-to-Read commands in different Ranks. 0 - Auto. Signed TAT delta
|
||||
is (Value - 128). Input value range of [1..255] will give a TAT delta range of
|
||||
[-127..127]
|
||||
**/
|
||||
UINT8 tWRDR;
|
||||
|
||||
/** Offset 0x0AE7 - tWRDD Delta
|
||||
/** Offset 0x0AD7 - tWRDD Delta
|
||||
Delay between Write-to-Read commands in different DIMMs. 0 - Auto. Signed TAT delta
|
||||
is (Value - 128). Input value range of [1..255] will give a TAT delta range of
|
||||
[-127..127]
|
||||
**/
|
||||
UINT8 tWRDD;
|
||||
|
||||
/** Offset 0x0AE8 - tWWSG Delta
|
||||
/** Offset 0x0AD8 - tWWSG Delta
|
||||
Delay between Write-to-Write commands in the same Bank Group. 0 - Auto. Signed TAT
|
||||
delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
|
||||
of [-127..127]
|
||||
**/
|
||||
UINT8 tWWSG;
|
||||
|
||||
/** Offset 0x0AE9 - tWWDG Delta
|
||||
/** Offset 0x0AD9 - tWWDG Delta
|
||||
Delay between Write-to-Write commands in different Bank Group. 0 - Auto. Signed
|
||||
TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta
|
||||
range of [-127..127]
|
||||
**/
|
||||
UINT8 tWWDG;
|
||||
|
||||
/** Offset 0x0AEA - tWWDR Delta
|
||||
/** Offset 0x0ADA - tWWDR Delta
|
||||
Delay between Write-to-Write commands in different Ranks. 0 - Auto. Signed TAT delta
|
||||
is (Value - 128). Input value range of [1..255] will give a TAT delta range of
|
||||
[-127..127]
|
||||
**/
|
||||
UINT8 tWWDR;
|
||||
|
||||
/** Offset 0x0AEB - tWWDD Delta
|
||||
/** Offset 0x0ADB - tWWDD Delta
|
||||
Delay between Write-to-Write commands in different DIMMs. 0 - Auto. Signed TAT delta
|
||||
is (Value - 128). Input value range of [1..255] will give a TAT delta range of
|
||||
[-127..127]
|
||||
**/
|
||||
UINT8 tWWDD;
|
||||
|
||||
/** Offset 0x0AEC - tRWSG Delta
|
||||
/** Offset 0x0ADC - tRWSG Delta
|
||||
Delay between Read-to-Write commands in the same Bank Group. 0 - Auto. Signed TAT
|
||||
delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
|
||||
of [-127..127]
|
||||
**/
|
||||
UINT8 tRWSG;
|
||||
|
||||
/** Offset 0x0AED - tRWDG Delta
|
||||
/** Offset 0x0ADD - tRWDG Delta
|
||||
Delay between Read-to-Write commands in different Bank Group. 0 - Auto. Signed TAT
|
||||
delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
|
||||
of [-127..127]
|
||||
**/
|
||||
UINT8 tRWDG;
|
||||
|
||||
/** Offset 0x0AEE - tRWDR Delta
|
||||
/** Offset 0x0ADE - tRWDR Delta
|
||||
Delay between Read-to-Write commands in different Ranks. 0 - Auto. Signed TAT delta
|
||||
is (Value - 128). Input value range of [1..255] will give a TAT delta range of
|
||||
[-127..127]
|
||||
**/
|
||||
UINT8 tRWDR;
|
||||
|
||||
/** Offset 0x0AEF - tRWDD Delta
|
||||
/** Offset 0x0ADF - tRWDD Delta
|
||||
Delay between Read-to-Write commands in different DIMMs. 0 - Auto. Signed TAT delta
|
||||
is (Value - 128). Input value range of [1..255] will give a TAT delta range of
|
||||
[-127..127]
|
||||
**/
|
||||
UINT8 tRWDD;
|
||||
|
||||
/** Offset 0x0AF0 - Reserved
|
||||
/** Offset 0x0AE0 - Reserved
|
||||
**/
|
||||
UINT8 Reserved94[13];
|
||||
|
||||
/** Offset 0x0AFD - Fake SAGV
|
||||
Fake SAGV: 0:Disabled, 1:Enabled
|
||||
/** Offset 0x0AED - PPR ForceRepair
|
||||
When Eanble, PPR will force repair some rows many times (90)
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PprForceRepair;
|
||||
|
||||
/** Offset 0x0AFE - Fake SAGV
|
||||
Fake SAGV: 0:Disabled, 1:Enabled
|
||||
$EN_DIS
|
||||
/** Offset 0x0AEE - PPR Repair Bank
|
||||
PPR repair Bank: User chooses to force repair specifc address
|
||||
**/
|
||||
UINT8 PprRepairBank;
|
||||
|
||||
/** Offset 0x0AFF - Reserved
|
||||
/** Offset 0x0AEF - Reserved
|
||||
**/
|
||||
UINT8 Reserved95[25];
|
||||
UINT8 Reserved95[33];
|
||||
} FSP_M_CONFIG;
|
||||
|
||||
/** Fsp M UPD Configuration
|
||||
|
|
@ -2915,11 +2916,11 @@ typedef struct {
|
|||
**/
|
||||
FSP_M_CONFIG FspmConfig;
|
||||
|
||||
/** Offset 0x0B18
|
||||
/** Offset 0x0B10
|
||||
**/
|
||||
UINT8 UnusedUpdSpace54[6];
|
||||
UINT8 UnusedUpdSpace56[6];
|
||||
|
||||
/** Offset 0x0B1E
|
||||
/** Offset 0x0B16
|
||||
**/
|
||||
UINT16 UpdTerminator;
|
||||
} FSPM_UPD;
|
||||
|
|
|
|||
|
|
@ -475,30 +475,26 @@ typedef struct {
|
|||
**/
|
||||
UINT8 ITbtPcieTunnelingForUsb4;
|
||||
|
||||
/** Offset 0x0150 - Reserved
|
||||
**/
|
||||
UINT8 Reserved13[4];
|
||||
|
||||
/** Offset 0x0154 - ITBTForcePowerOn Timeout value
|
||||
/** Offset 0x0150 - ITBTForcePowerOn Timeout value
|
||||
ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000.
|
||||
100 = 100 ms.
|
||||
**/
|
||||
UINT16 ITbtForcePowerOnTimeoutInMs;
|
||||
|
||||
/** Offset 0x0156 - ITbtConnectTopology Timeout value
|
||||
/** Offset 0x0152 - ITbtConnectTopology Timeout value
|
||||
ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range
|
||||
is 0-10000. 100 = 100 ms.
|
||||
**/
|
||||
UINT16 ITbtConnectTopologyTimeoutInMs;
|
||||
|
||||
/** Offset 0x0158 - ITBT DMA LTR
|
||||
/** Offset 0x0154 - ITBT DMA LTR
|
||||
TCSS DMA1, DMA2 LTR value
|
||||
**/
|
||||
UINT16 ITbtDmaLtr[2];
|
||||
|
||||
/** Offset 0x015C - Reserved
|
||||
/** Offset 0x0158 - Reserved
|
||||
**/
|
||||
UINT8 Reserved14[12];
|
||||
UINT8 Reserved13[16];
|
||||
|
||||
/** Offset 0x0168 - IEH Mode
|
||||
Integrated Error Handler Mode, 0: Bypass, 1: Enable
|
||||
|
|
@ -557,7 +553,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x0173 - Reserved
|
||||
**/
|
||||
UINT8 Reserved15;
|
||||
UINT8 Reserved14;
|
||||
|
||||
/** Offset 0x0174 - ISH GP GPIO Pin Muxing
|
||||
Determines ISH GP GPIO Pin muxing. See GPIO_*_MUXING_ISH_GP_x_GPIO_*. 'x' are GP_NUMBER
|
||||
|
|
@ -742,7 +738,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x0254 - Reserved
|
||||
**/
|
||||
UINT8 Reserved16;
|
||||
UINT8 Reserved15;
|
||||
|
||||
/** Offset 0x0255 - End of Post message
|
||||
Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
|
||||
|
|
@ -774,7 +770,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x0259 - Reserved
|
||||
**/
|
||||
UINT8 Reserved17[27];
|
||||
UINT8 Reserved16[27];
|
||||
|
||||
/** Offset 0x0274 - Power button debounce configuration
|
||||
Debounce time for PWRBTN in microseconds. For values not supported by HW, they will
|
||||
|
|
@ -831,7 +827,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x027F - Reserved
|
||||
**/
|
||||
UINT8 Reserved18;
|
||||
UINT8 Reserved17;
|
||||
|
||||
/** Offset 0x0280 - PCH Pm Slp S3 Min Assert
|
||||
SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.
|
||||
|
|
@ -957,7 +953,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x0294 - Reserved
|
||||
**/
|
||||
UINT8 Reserved19;
|
||||
UINT8 Reserved18;
|
||||
|
||||
/** Offset 0x0295 - PMC C10 dynamic threshold dajustment enable
|
||||
Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs
|
||||
|
|
@ -1128,7 +1124,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x0534 - Reserved
|
||||
**/
|
||||
UINT8 Reserved20[28];
|
||||
UINT8 Reserved19[28];
|
||||
|
||||
/** Offset 0x0550 - PCIE RP L1 Substates
|
||||
The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
|
||||
|
|
@ -1154,7 +1150,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x05B0 - Reserved
|
||||
**/
|
||||
UINT8 Reserved21[1525];
|
||||
UINT8 Reserved20[1525];
|
||||
|
||||
/** Offset 0x0BA5 - PCIE RP Enable Peer Memory Write
|
||||
This member describes whether Peer Memory Writes are enabled on the platform.
|
||||
|
|
@ -1184,7 +1180,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x0BBF - Reserved
|
||||
**/
|
||||
UINT8 Reserved22[12];
|
||||
UINT8 Reserved21[12];
|
||||
|
||||
/** Offset 0x0BCB - PCIe RootPort Power Gating
|
||||
Describes whether the PCI Express Power Gating for each root port is enabled by
|
||||
|
|
@ -1195,7 +1191,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x0BD7 - Reserved
|
||||
**/
|
||||
UINT8 Reserved23[49];
|
||||
UINT8 Reserved22[49];
|
||||
|
||||
/** Offset 0x0C08 - PCIE RP Ltr Max Snoop Latency
|
||||
Latency Tolerance Reporting, Max Snoop Latency.
|
||||
|
|
@ -1261,7 +1257,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x0D86 - Reserved
|
||||
**/
|
||||
UINT8 Reserved24[114];
|
||||
UINT8 Reserved23[114];
|
||||
|
||||
/** Offset 0x0DF8 - SPIn Device Mode
|
||||
Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available
|
||||
|
|
@ -1271,7 +1267,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x0DFF - Reserved
|
||||
**/
|
||||
UINT8 Reserved25[85];
|
||||
UINT8 Reserved24[85];
|
||||
|
||||
/** Offset 0x0E54 - SPIn Default Chip Select Mode HW/SW
|
||||
Sets Default CS Mode Hardware or Software. N represents controller index: SPI0,
|
||||
|
|
@ -1294,7 +1290,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x0E69 - Reserved
|
||||
**/
|
||||
UINT8 Reserved26[3];
|
||||
UINT8 Reserved25[3];
|
||||
|
||||
/** Offset 0x0E6C - Default BaudRate for each Serial IO UART
|
||||
Set default BaudRate Supported from 0 - default to 6000000
|
||||
|
|
@ -1334,7 +1330,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x0EB2 - Reserved
|
||||
**/
|
||||
UINT8 Reserved27[2];
|
||||
UINT8 Reserved26[2];
|
||||
|
||||
/** Offset 0x0EB4 - SerialIoUartRtsPinMuxPolicy
|
||||
Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
|
||||
|
|
@ -1368,7 +1364,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x0F17 - Reserved
|
||||
**/
|
||||
UINT8 Reserved28;
|
||||
UINT8 Reserved27;
|
||||
|
||||
/** Offset 0x0F18 - Serial IO I2C SDA Pin Muxing
|
||||
Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for
|
||||
|
|
@ -1391,7 +1387,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x0F60 - Reserved
|
||||
**/
|
||||
UINT8 Reserved29[148];
|
||||
UINT8 Reserved28[148];
|
||||
|
||||
/** Offset 0x0FF4 - TypeC port GPIO setting
|
||||
GPIO Ping number for Type C Aux orientation setting, use the GpioPad that is defined
|
||||
|
|
@ -1418,7 +1414,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x1030 - Reserved
|
||||
**/
|
||||
UINT8 Reserved30[2];
|
||||
UINT8 Reserved29[2];
|
||||
|
||||
/** Offset 0x1032 - Enable/Disable PMC-PD Solution
|
||||
This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution
|
||||
|
|
@ -1428,7 +1424,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x1033 - Reserved
|
||||
**/
|
||||
UINT8 Reserved31;
|
||||
UINT8 Reserved30;
|
||||
|
||||
/** Offset 0x1034 - TCSS Aux Orientation Override Enable
|
||||
Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
|
||||
|
|
@ -1504,16 +1500,33 @@ typedef struct {
|
|||
|
||||
/** Offset 0x106A - Reserved
|
||||
**/
|
||||
UINT8 Reserved32[4];
|
||||
UINT8 Reserved31[4];
|
||||
|
||||
/** Offset 0x106E - Touch Host Controller Assignment
|
||||
Assign THC 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0, 0x2:ThcAssignmentThc1
|
||||
**/
|
||||
UINT8 ThcAssignment[2];
|
||||
|
||||
/** Offset 0x1070 - Reserved
|
||||
/** Offset 0x1070 - Touch Host Controller Interrupt Pin Mux
|
||||
Set THC Pin Muxing Value if signal can be enabled on multiple pads. Refer to GPIO_*_MUXING_THC_SPIx_INTB_*
|
||||
for possible values.
|
||||
**/
|
||||
UINT8 Reserved33[349];
|
||||
UINT8 ThcInterruptPinMuxing[8];
|
||||
|
||||
/** Offset 0x1078 - Touch Host Controller Mode
|
||||
Switch between Intel THC protocol and Industry standard HID Over SPI protocol. 0x0:Thc, 0x1:Hid
|
||||
**/
|
||||
UINT8 ThcMode[2];
|
||||
|
||||
/** Offset 0x107A - Touch Host Controller Wake On Touch
|
||||
Based on this setting vGPIO for given THC will be in native mode, and additional
|
||||
_CRS for wake will be exposed in ACPI
|
||||
**/
|
||||
UINT8 ThcWakeOnTouch[2];
|
||||
|
||||
/** Offset 0x107C - Reserved
|
||||
**/
|
||||
UINT8 Reserved32[337];
|
||||
|
||||
/** Offset 0x11CD - PCHHOT# pin
|
||||
Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable
|
||||
|
|
@ -1578,7 +1591,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x11DF - Reserved
|
||||
**/
|
||||
UINT8 Reserved34[33];
|
||||
UINT8 Reserved33[33];
|
||||
|
||||
/** Offset 0x1200 - Enable USB2 ports
|
||||
Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
|
||||
|
|
@ -1607,7 +1620,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x121C - Reserved
|
||||
**/
|
||||
UINT8 Reserved35;
|
||||
UINT8 Reserved34;
|
||||
|
||||
/** Offset 0x121D - PCH USB OverCurrent mapping enable
|
||||
1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin
|
||||
|
|
@ -1634,7 +1647,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x1239 - Reserved
|
||||
**/
|
||||
UINT8 Reserved36[3];
|
||||
UINT8 Reserved35[3];
|
||||
|
||||
/** Offset 0x123C - xHCI High Idle Time LTR override
|
||||
Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting
|
||||
|
|
@ -1794,7 +1807,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x1361 - Reserved
|
||||
**/
|
||||
UINT8 Reserved37[4];
|
||||
UINT8 Reserved36[4];
|
||||
|
||||
/** Offset 0x1365 - Enable/Disable NPU Device
|
||||
Enable(Default): Enable NPU Device, Disable: Disable NPU Device
|
||||
|
|
@ -1816,7 +1829,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x1368 - Reserved
|
||||
**/
|
||||
UINT8 Reserved38;
|
||||
UINT8 Reserved37;
|
||||
|
||||
/** Offset 0x1369 - Skip Ssid Programming.
|
||||
When set to TRUE, silicon code will not do any SSID programming and platform code
|
||||
|
|
@ -1839,7 +1852,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x136E - Reserved
|
||||
**/
|
||||
UINT8 Reserved39[2];
|
||||
UINT8 Reserved38[2];
|
||||
|
||||
/** Offset 0x1370 - SVID SDID table Poniter.
|
||||
The address of the table of SVID SDID to customize each SVID SDID entry. This is
|
||||
|
|
@ -1855,7 +1868,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x137A - Reserved
|
||||
**/
|
||||
UINT8 Reserved40[10];
|
||||
UINT8 Reserved39[10];
|
||||
|
||||
/** Offset 0x1384 - LogoPixelHeight Address
|
||||
Address of LogoPixelHeight
|
||||
|
|
@ -1869,7 +1882,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x138C - Reserved
|
||||
**/
|
||||
UINT8 Reserved41[4];
|
||||
UINT8 Reserved40[4];
|
||||
|
||||
/** Offset 0x1390 - Blt Buffer Address
|
||||
Address of Blt buffer
|
||||
|
|
@ -1889,7 +1902,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x13A1 - Reserved
|
||||
**/
|
||||
UINT8 Reserved42;
|
||||
UINT8 Reserved41;
|
||||
|
||||
/** Offset 0x13A2 - Enable/Disable IGFX RenderStandby
|
||||
Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby
|
||||
|
|
@ -1899,7 +1912,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x13A3 - Reserved
|
||||
**/
|
||||
UINT8 Reserved43[3];
|
||||
UINT8 Reserved42[3];
|
||||
|
||||
/** Offset 0x13A6 - Enable/Disable PavpEnable
|
||||
Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable
|
||||
|
|
@ -1916,7 +1929,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x13A8 - Reserved
|
||||
**/
|
||||
UINT8 Reserved44[4];
|
||||
UINT8 Reserved43[4];
|
||||
|
||||
/** Offset 0x13AC - Intel Graphics VBT (Video BIOS Table) Size
|
||||
Size of Internal Graphics VBT Image
|
||||
|
|
@ -1931,7 +1944,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x13B1 - Reserved
|
||||
**/
|
||||
UINT8 Reserved45[11];
|
||||
UINT8 Reserved44[11];
|
||||
|
||||
/** Offset 0x13BC - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
|
||||
The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
|
||||
|
|
@ -1967,7 +1980,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x13C5 - Reserved
|
||||
**/
|
||||
UINT8 Reserved46[5];
|
||||
UINT8 Reserved45[5];
|
||||
|
||||
/** Offset 0x13CA - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states
|
||||
Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5
|
||||
|
|
@ -2001,7 +2014,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x13D1 - Reserved
|
||||
**/
|
||||
UINT8 Reserved47;
|
||||
UINT8 Reserved46;
|
||||
|
||||
/** Offset 0x13D2 - External Vnn Voltage Value that will be used in S0ix/Sx states
|
||||
Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420
|
||||
|
|
@ -2062,7 +2075,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x13DF - Reserved
|
||||
**/
|
||||
UINT8 Reserved48;
|
||||
UINT8 Reserved47;
|
||||
|
||||
/** Offset 0x13E0 - External V1P05 Icc Max Value
|
||||
Granularity of this setting is 1mA and maximal possible value is 500mA
|
||||
|
|
@ -2104,7 +2117,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x13EA - Reserved
|
||||
**/
|
||||
UINT8 Reserved49;
|
||||
UINT8 Reserved48;
|
||||
|
||||
/** Offset 0x13EB - PCH Unlock SideBand access
|
||||
The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before
|
||||
|
|
@ -2173,7 +2186,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x13F5 - Reserved
|
||||
**/
|
||||
UINT8 Reserved50[3];
|
||||
UINT8 Reserved49[3];
|
||||
|
||||
/** Offset 0x13F8 - CNVi RF_RESET pin muxing
|
||||
Select CNVi RF_RESET# pin depending on board routing. LP/P/M: GPP_A8 = 0x2942E408(default)
|
||||
|
|
@ -2190,7 +2203,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x1400 - Reserved
|
||||
**/
|
||||
UINT8 Reserved51;
|
||||
UINT8 Reserved50;
|
||||
|
||||
/** Offset 0x1401 - Enable Device 4
|
||||
Enable/disable Device 4
|
||||
|
|
@ -2207,7 +2220,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x1403 - Reserved
|
||||
**/
|
||||
UINT8 Reserved52;
|
||||
UINT8 Reserved51;
|
||||
|
||||
/** Offset 0x1404 - PCH HDA Verb Table Entry Number
|
||||
Number of Entries in Verb Table.
|
||||
|
|
@ -2216,7 +2229,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x1405 - Reserved
|
||||
**/
|
||||
UINT8 Reserved53[3];
|
||||
UINT8 Reserved52[3];
|
||||
|
||||
/** Offset 0x1408 - PCH HDA Verb Table Pointer
|
||||
Pointer to Array of pointers to Verb Table.
|
||||
|
|
@ -2242,7 +2255,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x1413 - Reserved
|
||||
**/
|
||||
UINT8 Reserved54[2];
|
||||
UINT8 Reserved53[2];
|
||||
|
||||
/** Offset 0x1415 - HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode
|
||||
HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode: 0: Disable, 1: Enable
|
||||
|
|
@ -2282,7 +2295,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x141B - Reserved
|
||||
**/
|
||||
UINT8 Reserved55[13];
|
||||
UINT8 Reserved54[13];
|
||||
|
||||
/** Offset 0x1428 - Pointer to ChipsetInit Binary
|
||||
ChipsetInit Binary Pointer.
|
||||
|
|
@ -2296,7 +2309,7 @@ typedef struct {
|
|||
|
||||
/** Offset 0x1434 - Reserved
|
||||
**/
|
||||
UINT8 Reserved56[36];
|
||||
UINT8 Reserved55[36];
|
||||
} FSP_S_CONFIG;
|
||||
|
||||
/** Fsp S UPD Configuration
|
||||
|
|
|
|||
|
|
@ -32,8 +32,9 @@ extern EFI_GUID gSiMemoryPlatformDataGuid;
|
|||
#define MAX_DDR5_CH 2
|
||||
#define MAX_DIMM 2
|
||||
|
||||
#define MAX_RANK_IN_CHANNEL (4)
|
||||
#define MAX_SDRAM_IN_DIMM (5)
|
||||
// Must be same or higher than the corresponding definitions in MrcGlobalDefinitions.h
|
||||
#define _MAX_RANK_IN_CHANNEL (4) ///< The maximum number of ranks per channel.
|
||||
#define _MAX_SDRAM_IN_DIMM (5) ///< The maximum number of SDRAMs per DIMM.
|
||||
|
||||
// Must match definitions in
|
||||
// Intel\OneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h
|
||||
|
|
@ -70,7 +71,7 @@ typedef struct _EFI_HOB_GUID_TYPE {
|
|||
#endif
|
||||
|
||||
///
|
||||
/// Defines taken from MRC to avoid having to include MrcInterface.h
|
||||
/// Defines taken from MRC so avoid having to include MrcInterface.h
|
||||
///
|
||||
|
||||
//
|
||||
|
|
@ -337,7 +338,7 @@ typedef struct {
|
|||
UINT16 PprForceRepairStatus; ///< PPR: Force Repair Status
|
||||
UINT16 PprRepairsSuccessful; ///< PPR: Counts of repair successes
|
||||
PPR_RESULT_COLUMNS_HOB PprErrorInfo; ///< PPR: Error location
|
||||
UINT8 PprAvailableResources[MAX_NODE][MAX_CH][MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]; ///< PPR available resources per device
|
||||
UINT8 PprAvailableResources[MAX_NODE][MAX_CH][_MAX_RANK_IN_CHANNEL][_MAX_SDRAM_IN_DIMM]; ///< PPR available resources per device
|
||||
} MEMORY_INFO_DATA_HOB;
|
||||
|
||||
/**
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue