working ipl.S for the vt526 and other 8601 via mainboards.
Current problem is it does not write-enable flash correctly.
This commit is contained in:
Ronald G. Minnich
parent
c5270ce7e7
commit
c0fa9a5321
1 changed files with 384 additions and 0 deletions
384
src/northbridge/via/vt8601/ipl.S
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384
src/northbridge/via/vt8601/ipl.S
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#include <asm.h>
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#include <cpu/p5/macros.h>
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#include <intel.h>
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/*
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*/
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#define DOC_WIN_SEG 0xfe00
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#define DOC_STACK_SEG 0x0400
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#define SPL_RAM_SEG 0x8000
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#define DOC_SPL_START_BLK 2 /* 0,1 for IPL */
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#define DOC_SPL_SIZE_IN_PAGE 126 /* 1 page = 512 bytes, total 63kB */
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/* wow, the usual way to to this hurts. So we do it our way:
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* 32-bit test not needed.
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*/
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/*#include <cpu/p5/start32.inc>*/
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.org 0xfe000
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.code16
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_start: jmp _realstart
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gdt: //GDT entry 0 (null segment)
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.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
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.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
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// GDT 1
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.word 0xffff, 0x0000 /* flat code segment */
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.byte 0x0, 0x9a, 0xcf, 0x0
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.word 0xffff, 0x0000 /* flat data segment */
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.byte 0x0, 0x92, 0xcf, 0x0
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gdtptr:
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.word 4*8-1
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.long gdt /* we know the offset */
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.long 0
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/* initialize registers */
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#define REG(a) a&0xfc, (a&0x3)|4
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register_table:
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.byte REG(0x78), 0x01
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.byte REG(0x68), 0x00
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.byte REG(0x6b), 0x00
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.byte REG(0x58), 0x88
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.byte REG(0x59), 0x88
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.byte REG(0x5a), 0x08
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.byte REG(0x5b), 0x10
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.byte REG(0x5c), 0x10
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.byte REG(0x5d), 0x10
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.byte REG(0x5e), 0x10
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.byte REG(0x5f), 0x10
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.byte REG(0x56), 0x10
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.byte REG(0x57), 0x10
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.byte REG(0x60), 0xff
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.byte REG(0x64), 0xee
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.byte REG(0x65), 0xee
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.byte REG(0x66), 0xee
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.byte REG(0x69), 0x04
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.byte REG(0x6a), 0x00
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.byte REG(0x6c), 0x00
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.byte REG(0x6d), 0x37
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// This extra set is redundant, but needed below.
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// LEAVE IT HERE.
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.byte REG(0x6c), 0x0
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.byte 0x0
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_realstart:
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cli
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movw %cs, %ax
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movw %ax, %es
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.byte 0x66 /* prefix */
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.byte 0x26
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.byte 0x0f, 0x01, 0x16 /* lgdt [es:offset]*/
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.word gdtptr - EXT(_start) /* offset in segment */
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movl %cr0, %eax
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andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
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orl $0x60000001, %eax /* CD, NW, PE = 1 */
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movl %eax, %cr0
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/* invalidate the cache */
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invd
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data32 ljmp $0x10, $.Lprotected
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.Lprotected:
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.code32
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movw $0x18, %bx
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movw %bx, %es
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movw %bx, %ds
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/*
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movw %bx, %es
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movw %bx, %fs
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movw %bx, %gs
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movw %bx, %ss
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*/
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// Registers
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// %esp holds the 0x80000000 pattern
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// %edx always hold $0xcf8
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// %esi holds 0
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// %edi holds 0x40000000
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// %bl is reused as needed.
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// store this constant in %esp
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movl $0x80000000, %esp
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/* make the flash writeable */
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/* select the south bridge, register 40 (base) */
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/* south bridge is device 7. 7 << 3 is 0x38 */
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movl %esp, %eax
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#define FLASHREG ((SUPERIO_DEVFN<<8) | 0x40)
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orw $FLASHREG, %ax
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mov $0xcf8,%dx
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outl %eax,%dx
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/* but 0x01 makes flash writeable. You need this for DoC */
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mov $0x0cfc,%dx
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inl %dx,%eax
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orl $0xc0000001, %eax
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outl %eax,%dx
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#define loop200 $0x5000
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#define loop100 $0x2500
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ram_set_registers:
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movl $register_table, %esi
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1:
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movl %esp, %eax
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orb (%esi), %al
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testb %al, %al
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jz done_ram_set_registers
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andb $0xf8, %dl
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outl %eax, %dx
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inc %esi
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orb (%esi), %dl
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inc %esi
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movb (%esi), %al
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outb %al, %dx
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// PCI_WRITE_CONFIG_BYTE
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inc %esi
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jmp 1b
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done_ram_set_registers:
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xorl %esi, %esi
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movl $0x4000000, %edi
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/* begin to initialize*/
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// I forget why we need this, but we do
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mov $0xa55a5aa5, %ecx
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mov %ecx, (%esi)
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mov %ecx, (%edi)
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// REMEMBER: 0xcf8 was set to 0x8000006c above. No need to set
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// again!
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// Also, remember: %edx has 0xcfc from the above loop!
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// that is the correct value!
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/* set NOP*/
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#define WRITE_6c(unused,val) movb val, %al ; outb %al, %dx
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WRITE_6c($0x6C, $0x01)
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/* wait 200us*/
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// You need to do the memory reference. That causes the nop cycle.
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mov (%esi), %ecx
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mov (%edi), %ecx
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DELAY(loop200)
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/* set precharge */
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WRITE_6c($0x6C, $0x02)
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/* dummy reads*/
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mov (%esi), %ecx
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mov (%edi), %ecx
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/* set CBR*/
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WRITE_6c($0x6C, $0x04)
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/* do 8 reads and wait 100us between each - from via*/
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movb $8, %bl
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eightreads:
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mov (%esi), %ecx
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mov (%edi), %ecx
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DELAY(loop100)
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dec %bl
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cmpb $0, %bl
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ja eightreads
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/* set MRS*/
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// 0x150 is cas2. We are now using 0x1d0, which is cas3
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WRITE_6c($0x6c, $0x03)
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movl $0x1d0, %ecx
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movl (%ecx), %ecx
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movl $0x40001d0, %ecx
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movl (%ecx), %ecx
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/* set to normal mode */
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WRITE_6c($0x6C, $0x00)
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movl $0x55aa55aa, %ecx
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mov %ecx, (%esi)
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mov (%esi), %ecx
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// Set the refresh rate.
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movb $0x68, %al
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movb $0xf8, %dl
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outl %eax, %dx
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addw $7, %dx
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movb $0x65, %al
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outb %al, %dx
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//CS_WRITE($0x6A, $0x65)
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// enable multi-page open
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inc %dl
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movb $1, %al
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outb %al, %dx
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//CS_WRITE($0x6B, $0x01)
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/* now for flash ... */
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/* NOTE: MUST NOT DESTROY %ecx! */
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/* INPUT: %al, the register. %ecx, the write data */
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/* Following code courtesy Ollie Lho: */
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/*
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* ipl.S: Initial Program Loader (IPL) for SiS 630 and M-System DoC Millennium
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*
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*
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* Copyright 2000 Silicon Integrated Systems Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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* Reference:
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* 1. SiS 630 Specification
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* 2. System Management Bus Specification Rev 1.1
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* 3. PC SDRAM Serial Presence Detect (SPD) Specification Rev 1.2B
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* 4. Booting From the DiskOnChip Millennium, M-Systems Application Note Ap-DOC-044
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* APR-2000, 93-SR-001-44-7L REV. 1.0
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*
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* $Id$
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*/
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#define DOC_WIN_SEG 0xfe00
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#define DOC_STACK 0x04000
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#define SPL_RAM 0x80000
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#define DOC_SPL_START_BLK 2 /* 0,1 for IPL */
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#define DOC_SPL_SIZE_IN_PAGE 126 /* 1 page = 512 bytes, total 63kB */
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ipl_start:
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#if 0
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/* stack and es already set. */
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/* O.K. we have DRAM now, so set up STACK for CALL/RET */
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movw $DOC_STACK_SEG, %ax
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movw %ax, %ss
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movw $SPL_RAM_SEG, %ax
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movw %ax, %es
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movl $DOC_STACK_SEG, %esp # set %sp
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#endif
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/* NOTE: in ollie's original code, %ds was at 0xfe00, i.e.
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* 0xfe000, i.e. base of DoC. We have to adjust for that when
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* we set %edi and %esi
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*/
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movl $DOC_STACK, %esp # set %sp
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movl $SPL_RAM, %edx # start of RAM
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xorl %ecx, %ecx # clear %ecx
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movl $0xfe800, %esi # point %si to CDSN Data area
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movl $0xff000, %edi # point %di to CDSN Control area
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movl $DOC_SPL_START_BLK, %ebp # start page of LinuxBIOS
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movb $0x84, %al # Reset DOC Millennium
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call doc_reset
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movb $0x85, %al # Turn into Normal Mode
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call doc_reset
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read_next_page:
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movl $0xff000, %edi # point %di to CDSN Control area
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flash_command:
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movb $0x03, 0x04(%edi) # start command cycle
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movb $0x00, (%esi) # issue flash command Read00
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call doc_cycle_end
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movw %bp, %bx # %bp is current page number
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flash_address:
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shll $0x08, %ebx
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movb $0x03, %cl # this one is DANGEROUS but I am
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# sure the upper 3 bytes == 0x00
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movb $0x05, 0x04(%edi) # start address cycle
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0:
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movb %bl, (%esi) # write address to CDSNIO
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shrw $0x08, %bx # shift next address byte
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loop 0b
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call doc_cycle_end
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wait_for_flash_ready:
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/* delay by reding NOP register before polling the FLASH READY bit,
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this is inlined to save a call/ret pair */
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doc_delay:
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movb $0x04, %cl # this one is DANGEROUS but I am
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# sure the upper 3 bytes == 0x00
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0:
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movb 0x20(%edi), %al # read DOC NOP retisger
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loop 0b # four times
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testb $0x80, 0x04(%edi) # is flash ready ?
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jz wait_for_flash_ready
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movb 0x1d(%edi), %al # init read pipeline
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movw $0x100, %cx # 1 page = 512 bytes
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movl $0xfe800, %esi # point %si to CDSN Data area
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movl %edx, %edi # restore saved current destination
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rep
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movsw
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movl %edi, %edx # save current destination
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incw %bp # increse current page number
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cmpw $128, %bp # moved 63 KB ??
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jl read_next_page # no, read next page
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sis630ipl_end:
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# jmp to 8000:0000, where SPL
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# (LinuxBIOS) starts in RAM
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# ljmp $0x10,$0x8000
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jmp spl_vector
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doc_reset:
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/* Input: AL = value write to DOC_CONTROL register
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Clobberd: CX */
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movb %al, 0x02(%edi) # write DoC Control retister
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movb %al, 0x02(%edi) # twice
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ret # End of doc_reset
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doc_cycle_end:
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movb $0x00, 0x1e(%edi) # flush write pepeline
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movb $0x01, 0x04(%edi) # end command cycle
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ret
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/* we don't need these. We only do I/O to MCR 0 */
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#if 0
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pci_write_dword:
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mov $0,%ah
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mov $0x80000000,%edx
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or %ax,%dx
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mov %edx,%eax
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mov $0x0cf8,%dx
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outl %eax,%dx
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mov $0x0fc,%dl
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mov %ecx, %eax
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outl %eax,%dx
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RETSP
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pci_read_dword:
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mov $0,%ah
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mov $0x80000000,%edx
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or %ax,%dx
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mov %edx,%eax
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mov $0x0cf8,%dx
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outl %eax,%dx
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mov $0x0fc,%dl
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inl %dx, %eax
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mov %eax, %ecx
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RETSP
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#endif
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.org 0xfe1f0
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reset_vector:
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.byte 0xea #jump to fe00:0000, where IPL
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.word 0x0000, DOC_WIN_SEG #starts in DoC
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.code32
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spl_vector:
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invd
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jmpl $0x10, $0x80000
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# jumpl $0x80000
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# put this here to buy some room
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pad: .byte 0,0
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