From c0dd822babee3d766eff1735687d14e63380f702 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 10 Jun 2014 10:05:03 -0700 Subject: [PATCH] samus: Minor fixes for P1.9 boards - Put SSD into reset on transition to S3/S5 to prevent leakage - Fix GPIO number for wlan disable used in smihandler - Enable generic hub driver in libpayload - Fix comment in devicetree about S0ix BUG=chrome-os-partner:28502 BRANCH=None TEST=Build and boot on samus Change-Id: Idce566d0f22622d36697be54ab51cacb576c5d6d Signed-off-by: Duncan Laurie Reviewed-on: https://chromium-review.googlesource.com/203185 Reviewed-by: Aaron Durbin --- payloads/libpayload/configs/config.samus | 1 + src/mainboard/google/samus/devicetree.cb | 2 +- src/mainboard/google/samus/smihandler.c | 8 ++++++-- 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/configs/config.samus b/payloads/libpayload/configs/config.samus index e3ce6a392f..99881cbfa0 100644 --- a/payloads/libpayload/configs/config.samus +++ b/payloads/libpayload/configs/config.samus @@ -69,6 +69,7 @@ CONFIG_LP_USB_HID=y CONFIG_LP_USB_HUB=y CONFIG_LP_USB_MSC=y CONFIG_LP_USB_PCI=y +CONFIG_LP_USB_GEN_HUB=y # CONFIG_LP_USB_MEMORY is not set # CONFIG_LP_BIG_ENDIAN is not set CONFIG_LP_LITTLE_ENDIAN=y diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb index ce13a1daf2..95ab44be1e 100644 --- a/src/mainboard/google/samus/devicetree.cb +++ b/src/mainboard/google/samus/devicetree.cb @@ -52,7 +52,7 @@ chip soc/intel/broadwell # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP register "icc_clock_disable" = "0x013b0000" - # Enable S0ix + # Disable S0ix for now register "s0ix_enable" = "0" device cpu_cluster 0 on diff --git a/src/mainboard/google/samus/smihandler.c b/src/mainboard/google/samus/smihandler.c index 8a8a150b70..150bec2884 100644 --- a/src/mainboard/google/samus/smihandler.c +++ b/src/mainboard/google/samus/smihandler.c @@ -32,8 +32,8 @@ #include #include "ec.h" -/* GPIO46 controls the WLAN_DISABLE_L signal. */ -#define GPIO_WLAN_DISABLE_L 46 +#define GPIO_SSD_RESET_L 47 +#define GPIO_WLAN_DISABLE_L 42 #define GPIO_LTE_DISABLE_L 59 int mainboard_io_trap_handler(int smif) @@ -103,6 +103,8 @@ void mainboard_smi_sleep(u8 slp_typ) 1, USB_CHARGE_MODE_DISABLED); } + /* Put SSD in reset to prevent leak. */ + set_gpio(GPIO_SSD_RESET_L, 0); /* Prevent leak from standby rail to WLAN rail in S3. */ set_gpio(GPIO_WLAN_DISABLE_L, 0); /* Disable LTE */ @@ -119,6 +121,8 @@ void mainboard_smi_sleep(u8 slp_typ) 1, USB_CHARGE_MODE_DISABLED); } + /* Put SSD in reset to prevent leak. */ + set_gpio(GPIO_SSD_RESET_L, 0); /* Prevent leak from standby rail to WLAN rail in S5. */ set_gpio(GPIO_WLAN_DISABLE_L, 0); /* Disable LTE */