From c09352d58d4d815735ae76594633f0ba62e327c3 Mon Sep 17 00:00:00 2001 From: Jeremy Compostella Date: Mon, 12 Jan 2026 10:40:02 -0800 Subject: [PATCH] soc/intel/pantherlake: Update PS1 threshold to the latest recommendations Update the PS1 threshold values for VR_DOMAIN_IA, VR_DOMAIN_GT, and VR_DOMAIN_SA from 20 A to 15 A, following the recommendations in the Panther Lake H Platform Design Guide (Draft > 2.1). This change ensures that power state thresholds are consistent with the most recent platform specifications, improving accuracy and system behavior under varying power conditions. TEST=Fatcat device boots to OS. Change-Id: I358d4d94c3800ff5b658cb875c90ee7409d86377 Signed-off-by: Jeremy Compostella Reviewed-on: https://review.coreboot.org/c/coreboot/+/90727 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/pantherlake/chipset_ptl.cb | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb index ccd727d6cd..fb78b88659 100644 --- a/src/soc/intel/pantherlake/chipset_ptl.cb +++ b/src/soc/intel/pantherlake/chipset_ptl.cb @@ -82,11 +82,11 @@ chip soc/intel/pantherlake register "tdc_time_window_ms[VR_DOMAIN_IA]" = "28000" # Set the power state thresholds according to document 813278 - # Panther Lake H Platform - Design Guide - Rev 2.0 + # Panther Lake H Platform - Design Guide - Draft > 2.1 register "ps1_threshold" = "{ - [VR_DOMAIN_IA] = 20 * 4, - [VR_DOMAIN_GT] = 20 * 4, - [VR_DOMAIN_SA] = 20 * 4 + [VR_DOMAIN_IA] = 15 * 4, + [VR_DOMAIN_GT] = 15 * 4, + [VR_DOMAIN_SA] = 15 * 4 }" register "ps2_threshold" = "{ [VR_DOMAIN_IA] = 5 * 4,