diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index e8f87b4d54..e2ba45ee16 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -103,7 +103,7 @@ STAGE0_LIB_SRC       = uart8250.c mem.c lar.c delay.c vtxprintf.c \
 		       vsprintf.c console.c string.c $(DECOMPRESSORS)
 STAGE0_ARCH_X86_SRC  = stage1.c serial.c \
 		       udelay_io.c mc146818rtc.c post_code.c \
-			pci_ops_conf1.c resourcemap.c 
+			pci_ops_conf1.c 
 # speaker.c \
 
 ifeq ($(CONFIG_PAYLOAD_ELF_LOADER),y)
diff --git a/mainboard/amd/dbm690t/Makefile b/mainboard/amd/dbm690t/Makefile
index 96d438ef59..c41c146291 100644
--- a/mainboard/amd/dbm690t/Makefile
+++ b/mainboard/amd/dbm690t/Makefile
@@ -34,6 +34,7 @@ INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 			$(src)/northbridge/amd/k8/reset_test.c \
 			$(src)/northbridge/amd/k8/coherent_ht.c \
 			$(src)/northbridge/amd/k8/incoherent_ht.c \
+			$(src)/northbridge/amd/k8/coherent_ht.c \
 			$(src)/arch/x86/pci_ops_conf1.c \
 			$(src)/arch/x86/stage1_mtrr.c \
 			$(src)/arch/x86/amd/model_fxx/dualcore.c \
diff --git a/mainboard/amd/serengeti/Makefile b/mainboard/amd/serengeti/Makefile
index 79462668ff..c2d1dde745 100644
--- a/mainboard/amd/serengeti/Makefile
+++ b/mainboard/amd/serengeti/Makefile
@@ -26,6 +26,7 @@ STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \
 			$(src)/arch/x86/stage1_mtrr.c \
 			$(src)/arch/x86/amd/model_fxx/dualcore_id.c \
 			$(src)/arch/x86/amd/model_fxx/stage1.c \
+			$(src)/arch/x86/resourcemap.c \
 			$(src)/northbridge/amd/k8/get_nodes.c \
 			$(src)/northbridge/amd/k8/libstage1.c \
 			$(src)/southbridge/amd/amd8111/stage1_smbus.c \
diff --git a/mainboard/amd/serengeti/dts b/mainboard/amd/serengeti/dts
index b8bb3417bf..5aee35f5f6 100644
--- a/mainboard/amd/serengeti/dts
+++ b/mainboard/amd/serengeti/dts
@@ -32,13 +32,37 @@
 		pci0@18,0 {
 			/config/("northbridge/amd/k8/pci");
 			pci@0,0 {
-				/config/("southbridge/amd/amd8111/amd8111.dts");
+				/config/("southbridge/amd/amd8111/pci.dts");
+				pci@1,0{
+					/config/("southbridge/amd/amd8111/nic.dts");
+				};
+				pci@0,0{
+					/config/("southbridge/amd/amd8111/usb.dts");
+				};
+				pci@0,1{
+					/config/("southbridge/amd/amd8111/usb.dts");
+				};
+				pci@0,2{
+					/config/("southbridge/amd/amd8111/usb2.dts");
+				};
 			};
-			pci@4,0 {
+			pci@7,0 {
+				/config/("southbridge/amd/amd8111/lpc.dts");
+			};
+			pci@7,1 {
 				/config/("southbridge/amd/amd8111/ide.dts");
 			};
-			pci@5,0 {
-				/config/("southbridge/amd/amd8111/nic.dts");
+			pci@7,2 {
+				/config/("southbridge/amd/amd8111/smbus.dts");
+			};
+			pci@7,3 {
+				/config/("southbridge/amd/amd8111/acpi.dts");
+			};
+			pci@7,5 {
+				/config/("southbridge/amd/amd8111/ac97audio.dts");
+			};
+			pci@7,6 {
+				/config/("southbridge/amd/amd8111/ac97modem.dts");
 			};
 		};
 		pci1@18,0 {
diff --git a/southbridge/amd/amd8111/amd8111.c b/southbridge/amd/amd8111/amd8111.c
index 3b22fa1ce8..468cc10dcf 100644
--- a/southbridge/amd/amd8111/amd8111.c
+++ b/southbridge/amd/amd8111/amd8111.c
@@ -92,15 +92,3 @@ void amd8111_enable(struct device * dev)
 	}
 }
 
-struct device_operations amd8111 = {
-	.id = {.type = DEVICE_ID_PCI,
-		{.pci = {.vendor = PCI_VENDOR_ID_AMD,
-			 .device = PCI_DEVICE_ID_AMD_8111_PCI}}},
-	.constructor		 = default_device_constructor,
-	.phase3_scan		 = 0,
-	.phase4_enable_disable	 = amd8111_enable,
-	.phase4_read_resources	 = pci_dev_read_resources,
-	.phase4_set_resources	 = pci_dev_set_resources,
-	.phase6_init		 = NULL,
-	.ops_pci		 = &pci_dev_ops_pci,
-};
diff --git a/southbridge/amd/amd8111/amd8111.dts b/southbridge/amd/amd8111/amd8111.dts
deleted file mode 100644
index 62eb4c7a26..0000000000
--- a/southbridge/amd/amd8111/amd8111.dts
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-{
-	device_operations = "amd8111";
-};
diff --git a/southbridge/amd/amd8111/pci.dts b/southbridge/amd/amd8111/pci.dts
index 951601798f..3c17e1f769 100644
--- a/southbridge/amd/amd8111/pci.dts
+++ b/southbridge/amd/amd8111/pci.dts
@@ -20,4 +20,5 @@
 
 {
 	device_operations = "amd8111_pci";
+	bridge;
 };
diff --git a/southbridge/amd/amd8111/usb.c b/southbridge/amd/amd8111/usb.c
index e366bf40c0..8f501be076 100644
--- a/southbridge/amd/amd8111/usb.c
+++ b/southbridge/amd/amd8111/usb.c
@@ -50,6 +50,7 @@ struct device_operations amd8111_usb = {
 			      .device = PCI_DEVICE_ID_AMD_8111_USB}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan		 = scan_static_bus,
+	.phase4_enable_disable           = amd8111_enable,
 	.phase4_read_resources	 = pci_dev_read_resources,
 	.phase4_set_resources	 = pci_dev_set_resources,
 	.phase5_enable_resources = pci_dev_enable_resources,