UPSTREAM: Add newlines at the end of all coreboot files

BUG=None
BRANCH=None
TEST=None

Change-Id: I56587a151b4c7bb0a2e71698799d4ef9dd2c436a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15974
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/366301
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Martin Roth 2016-07-28 16:32:56 -06:00 committed by chrome-bot
commit bf5c2e059f
38 changed files with 43 additions and 37 deletions

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@ -106,4 +106,4 @@ unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current)
current += 8;
return current;
}
}

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@ -43,4 +43,4 @@ After that, there's a cascade of small FETs and resistors in that region, eventu
SuperIO pin 81 (VSBGATE#) enables the standby voltage rails when set LOW.
VSBGATE# is reset on every assertion of PWRGOOD.
Setting SuperIO LDN 9 CRF4 bits 1 or 0 (or both) to 0 disables NICB.
Setting SuperIO LDN 9 CRF4 bits 1 or 0 (or both) to 0 disables NICB.

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@ -78,4 +78,4 @@ void bootblock_mainboard_init(void)
*/
#endif
}
}
}

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@ -78,4 +78,4 @@ void bootblock_mainboard_init(void)
*/
#endif
}
}
}

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@ -106,4 +106,4 @@ unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current)
current += 8;
return current;
}
}

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@ -43,4 +43,4 @@ After that, there's a cascade of small FETs and resistors in that region, eventu
SuperIO pin 81 (VSBGATE#) enables the standby voltage rails when set LOW.
VSBGATE# is reset on every assertion of PWRGOOD.
Setting SuperIO LDN 9 CRF4 bits 1 or 0 (or both) to 0 disables NICB.
Setting SuperIO LDN 9 CRF4 bits 1 or 0 (or both) to 0 disables NICB.

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@ -61,4 +61,4 @@ unsigned long acpi_fill_madt(unsigned long current)
current = acpi_madt_irq_overrides(current);
return current;
}
}

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@ -1,3 +1,3 @@
{
.dramtype= UNUSED
},
},

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@ -1,3 +1,3 @@
{
.dramtype= UNUSED
},
},

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@ -1,3 +1,3 @@
{
.dramtype= UNUSED
},
},

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@ -1,3 +1,3 @@
{
.dramtype= UNUSED
},
},

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@ -1,3 +1,3 @@
{
.dramtype= UNUSED
},
},

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@ -1,3 +1,3 @@
{
.dramtype= UNUSED
},
},

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@ -1,3 +1,3 @@
{
.dramtype= UNUSED
},
},

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@ -13,4 +13,4 @@
## GNU General Public License for more details.
##
ramstage-y += irqroute.c
ramstage-y += irqroute.c

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@ -6,4 +6,4 @@
* This file is included by lpc.asl in the southbridge directory.
* It is intended to be used to include any embedded controller
* specific ASL.
*/
*/

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@ -14,4 +14,4 @@ power_management_beeps=Enable
low_battery_beep=Enable
sata_mode=AHCI
hybrid_graphics_mode=Integrated Only
gfx_uma_size=32M
gfx_uma_size=32M

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@ -14,4 +14,4 @@ fn_ctrl_swap=Disable
sticky_fn=Disable
trackpoint=Enable
hyper_threading=Enable
hybrid_graphics_mode=Integrated Only
hybrid_graphics_mode=Integrated Only

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@ -14,4 +14,4 @@ fn_ctrl_swap=Disable
sticky_fn=Disable
trackpoint=Enable
hyper_threading=Enable
hybrid_graphics_mode=Integrated Only
hybrid_graphics_mode=Integrated Only

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@ -15,4 +15,4 @@ sticky_fn=Disable
trackpoint=Enable
hyper_threading=Enable
backlight=Both
hybrid_graphics_mode=Integrated Only
hybrid_graphics_mode=Integrated Only

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@ -15,4 +15,4 @@ sticky_fn=Disable
trackpoint=Enable
hyper_threading=Enable
backlight=Both
hybrid_graphics_mode=Integrated Only
hybrid_graphics_mode=Integrated Only

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@ -13,4 +13,4 @@ sticky_fn=Disable
power_management_beeps=Enable
low_battery_beep=Enable
sata_mode=AHCI
gfx_uma_size=32M
gfx_uma_size=32M

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@ -13,4 +13,4 @@
## GNU General Public License for more details.
##
ramstage-y += irqroute.c
ramstage-y += irqroute.c