From bf148cae0a1626c4dfb11bfd22fc19029284aa66 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 6 Oct 2025 11:23:57 +0200 Subject: [PATCH] lib/dimm_info_util.c: Handle 16-bit memory bus extension for ECC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some silicon initialization modules, like OpenSIL report bus width extension as 16 bits for ECC for DDR5 memories. Handle this case correctly for DDR5 and LPDDR5 memories by reporting appropriate bitfield of the SPD width. This field is used later by coreboot to calculate the bus extension again, which results in 16bit extension for ECC. Change-Id: Ia0a9c221a5d047dd7feb212027f5da2399ccb8e1 Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/89482 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/lib/dimm_info_util.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/lib/dimm_info_util.c b/src/lib/dimm_info_util.c index d16cb46d0a..6ca707c542 100644 --- a/src/lib/dimm_info_util.c +++ b/src/lib/dimm_info_util.c @@ -45,6 +45,13 @@ uint8_t smbios_bus_width_to_spd_width(uint8_t ddr_type, uint16_t total_width, else out |= SPD_ECC_8BIT; break; + case 16: + if (ddr_type == MEMORY_TYPE_DDR5 || ddr_type == MEMORY_TYPE_LPDDR5) + out |= SPD_ECC_8BIT_LP5_DDR5; + else + printk(BIOS_NOTICE, "Unknown number of extension bits %hu\n", + extension_bits); + break; case 0: /* No extension bits */ break;