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acpi: Change Processor ACPI Name (Intel only)

Browse source 
The ACPI Spec 2.0 states, that Processor declarations should be made
within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated
and is removed here for Intel CPUs only.

Tested on:
* X11SSH (Kabylake)
* CFL Platform
* Asus P8Z77-V LX2 and Windows 10

FWTS does not return FAIL anymore on ACPI tests

Tested-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: Ib101ed718f90f9056d2ecbc31b13b749ed1fc438
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Christian Walter 2019-12-18 15:07:59 +01:00 • committed by Nico Huber
commit be3979c873
30 changed files with 140 additions and 137 deletions
Download patch file Download diff file Expand all files Collapse all files

4
src/arch/x86/Kconfig
View file

@ -254,11 +254,11 @@ config ACPI_HAVE_PCAT_8259
config ACPI_CPU_STRING
string
default "\\_PR.CP%02d"
default "\\_SB.CP%02d"
depends on HAVE_ACPI_TABLES
help
Sets the ACPI name string in the processor scope as written by
the acpigen function. Default is \_PR.CPxx. Note that you need
the acpigen function. Default is \_SB.CPxx. Note that you need
the \ escape character in the string.
config COLLECT_TIMESTAMPS_NO_TSC

4
src/arch/x86/acpigen.c
View file

@ -340,7 +340,7 @@ void acpigen_write_scope(const char *name)
void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len)
{
/*
Processor (\_PR.CPcpuindex, cpuindex, pblock_addr, pblock_len)
Processor (\_SB.CPcpuindex, cpuindex, pblock_addr, pblock_len)
{
*/
char pscope[16];
@ -376,7 +376,7 @@ void acpigen_write_processor_cnot(const unsigned int number_of_cores)
{
int core_id;
acpigen_write_method("\\_PR.CNOT", 1);
acpigen_write_method("\\_SB.CNOT", 1);
for (core_id = 0; core_id < number_of_cores; core_id++) {
char buffer[DEVICE_PATH_MAX];
snprintf(buffer, sizeof(buffer), CONFIG_ACPI_CPU_STRING,

8
src/cpu/intel/common/acpi/cpu.asl
View file

@ -13,22 +13,22 @@
*/
/* These come from the dynamically created CPU SSDT */
External (\_PR.CNOT, MethodObj)
External (\_SB.CNOT, MethodObj)
/* Notify OS to re-read CPU tables */
Method (PNOT)
{
\_PR.CNOT (0x81)
\_SB.CNOT (0x81)
}
/* Notify OS to re-read CPU _PPC limit */
Method (PPCN)
{
\_PR.CNOT (0x80)
\_SB.CNOT (0x80)
}
/* Notify OS to re-read Throttle Limit tables */
Method (TNOT)
{
\_PR.CNOT (0x82)
\_SB.CNOT (0x82)
}

2
src/cpu/intel/haswell/acpi.c
View file

@ -317,7 +317,7 @@ void generate_cpu_entries(struct device *device)
plen = 0;
}
/* Generate processor \_PR.CPUx */
/* Generate processor \_SB.CPUx */
acpigen_write_processor(
(cpuID-1)*cores_per_package+coreID-1,
pcontrol_blk, plen);

2
src/cpu/intel/model_2065x/acpi.c
View file

@ -309,7 +309,7 @@ void generate_cpu_entries(struct device *device)
plen = 0;
}
/* Generate processor \_PR.CPUx */
/* Generate processor \_SB.CPUx */
acpigen_write_processor(
(cpuID-1)*cores_per_package+coreID-1,
pcontrol_blk, plen);

2
src/cpu/intel/model_206ax/acpi.c
View file

@ -312,7 +312,7 @@ void generate_cpu_entries(struct device *device)
plen = 0;
}
/* Generate processor \_PR.CPUx */
/* Generate processor \_SB.CPUx */
acpigen_write_processor(
(cpuID-1)*cores_per_package+coreID-1,
pcontrol_blk, plen);

2
src/cpu/intel/speedstep/acpi.c
View file

@ -124,7 +124,7 @@ void generate_cpu_entries(struct device *device)
plen = 0;
}
/* Generate processor \_PR.CPUx. */
/* Generate processor \_SB.CPUx. */
acpigen_write_processor(
cpuID * cores_per_package + coreID - 1,
pcontrol_blk, plen);

16
src/cpu/intel/speedstep/acpi/cpu.asl
View file

@ -12,20 +12,20 @@
*/
/* These come from the dynamically created CPU SSDT */
External (\_PR.CNOT, MethodObj)
External (\_PR_.CP00, DeviceObj)
External (\_PR_.CP00._PPC)
External (\_PR_.CP01._PPC)
External (\_SB.CNOT, MethodObj)
External (\_SB_.CP00, DeviceObj)
External (\_SB_.CP00._PPC)
External (\_SB_.CP01._PPC)
Method (PNOT)
{
If (MPEN) {
\_PR.CNOT (0x80) // _PPC
\_SB.CNOT (0x80) // _PPC
Sleep(100)
\_PR.CNOT (0x81) // _CST
\_SB.CNOT (0x81) // _CST
} Else { // UP
Notify (\_PR_.CP00, 0x80)
Notify (\_SB_.CP00, 0x80)
Sleep(0x64)
Notify(\_PR_.CP00, 0x81)
Notify(\_SB_.CP00, 0x81)
}
}

10
src/ec/quanta/ene_kb3940q/acpi/ec.asl
View file

@ -18,7 +18,7 @@
* re-evaluate their _PPC and _CST tables.
*/
External (\_PR.CP00._PPC, IntObj)
External (\_SB.CP00._PPC, IntObj)
Device (EC0)
{
@ -146,12 +146,12 @@ Device (EC0)
And(Local0, Ones, Local0)
// Find and program number of P-States
Store (SizeOf (\_PR.CP00._PSS), MPST)
Store (SizeOf (\_SB.CP00._PSS), MPST)
Store ("Programming number of P-states: ", Debug)
Store (MPST, Debug)
// Find and program the current P-State
Store(\_PR.CP00._PPC, NPST)
Store(\_SB.CP00._PPC, NPST)
Store ("Programming Current P-state: ", Debug)
Store (NPST, Debug)
}
@ -190,7 +190,7 @@ Device (EC0)
{
Store ("Pstate Event 0x0E", Debug)
Store(\_PR.CP00._PPC, Local0)
Store(\_SB.CP00._PPC, Local0)
Subtract(PPCM, 0x01, Local1)
If(LLess(Local0, Local1)) {
@ -205,7 +205,7 @@ Device (EC0)
Method (_Q0F)
{
Store ("Pstate Event 0x0F", Debug)
Store(\_PR.CP00._PPC, Local0)
Store(\_SB.CP00._PPC, Local0)
If(Local0) {
Decrement(Local0)

2
src/mainboard/getac/p470/acpi/ec.asl
View file

@ -99,7 +99,7 @@ Device(EC0)
// EC Query methods, called upon SCI interrupts.
Method (_Q01, 0)
{
Notify (\_PR.CP00, 0x80)
Notify (\_SB.CP00, 0x80)
If(ADP) {
Store(1, \_SB.AC.ACST)
TRAP(0xe3)

10
src/mainboard/getac/p470/acpi/platform.asl
View file

@ -89,15 +89,15 @@ Method(_WAK,1)
// Windows XP SP2 P-State restore
If (LAnd(LEqual(OSYS, 2002), And(CFGD, 1))) {
If (LGreater(\_PR.CP00._PPC, 0)) {
Subtract(\_PR.CP00._PPC, 1, \_PR.CP00._PPC)
If (LGreater(\_SB.CP00._PPC, 0)) {
Subtract(\_SB.CP00._PPC, 1, \_SB.CP00._PPC)
PNOT()
Add(\_PR.CP00._PPC, 1, \_PR.CP00._PPC)
Add(\_SB.CP00._PPC, 1, \_SB.CP00._PPC)
PNOT()
} Else {
Add(\_PR.CP00._PPC, 1, \_PR.CP00._PPC)
Add(\_SB.CP00._PPC, 1, \_SB.CP00._PPC)
PNOT()
Subtract(\_PR.CP00._PPC, 1, \_PR.CP00._PPC)
Subtract(\_SB.CP00._PPC, 1, \_SB.CP00._PPC)
PNOT()
}
}

4
src/mainboard/getac/p470/acpi/thermal.asl
View file

@ -73,9 +73,9 @@ Scope (\_TZ)
Method (_PSL, 0, Serialized)
{
If (MPEN) {
Return (Package() {\_PR.CP00, \_PR.CP01})
Return (Package() {\_SB.CP00, \_SB.CP01})
}
Return (Package() {\_PR.CP00})
Return (Package() {\_SB.CP00})
}
// TC1 value for passive cooling

38
src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl
View file

@ -41,11 +41,11 @@
#define DPTF_CPU_ACTIVE_AC4 50
#endif
External (\_PR.CP00._TSS, MethodObj)
External (\_PR.CP00._TPC, MethodObj)
External (\_PR.CP00._PTC, PkgObj)
External (\_PR.CP00._TSD, PkgObj)
External (\_PR.CP00._PSS, MethodObj)
External (\_SB.CP00._TSS, MethodObj)
External (\_SB.CP00._TPC, MethodObj)
External (\_SB.CP00._PTC, PkgObj)
External (\_SB.CP00._TSD, PkgObj)
External (\_SB.CP00._PSS, MethodObj)
Device (B0DB)
{
@ -66,8 +66,8 @@ Device (B0DB)
Method (_TSS)
{
If (CondRefOf (\_PR.CP00._TSS)) {
Return (\_PR.CP00._TSS)
If (CondRefOf (\_SB.CP00._TSS)) {
Return (\_SB.CP00._TSS)
} Else {
Return (Package ()
{
@ -78,8 +78,8 @@ Device (B0DB)
Method (_TPC)
{
If (CondRefOf (\_PR.CP00._TPC)) {
Return (\_PR.CP00._TPC)
If (CondRefOf (\_SB.CP00._TPC)) {
Return (\_SB.CP00._TPC)
} Else {
Return (0)
}
@ -87,8 +87,8 @@ Device (B0DB)
Method (_PTC)
{
If (CondRefOf (\_PR.CP00._PTC)) {
Return (\_PR.CP00._PTC)
If (CondRefOf (\_SB.CP00._PTC)) {
Return (\_SB.CP00._PTC)
} Else {
Return (Package ()
{
@ -100,8 +100,8 @@ Device (B0DB)
Method (_TSD)
{
If (CondRefOf (\_PR.CP00._TSD)) {
Return (\_PR.CP00._TSD)
If (CondRefOf (\_SB.CP00._TSD)) {
Return (\_SB.CP00._TSD)
} Else {
Return (Package ()
{
@ -112,8 +112,8 @@ Device (B0DB)
Method (_TDL)
{
If (CondRefOf (\_PR.CP00._TSS)) {
Store (SizeOf (\_PR.CP00._TSS ()), Local0)
If (CondRefOf (\_SB.CP00._TSS)) {
Store (SizeOf (\_SB.CP00._TSS ()), Local0)
Decrement (Local0)
Return (Local0)
} Else {
@ -140,8 +140,8 @@ Device (B0DB)
Method (_PSS)
{
If (CondRefOf (\_PR.CP00._PSS)) {
Return (\_PR.CP00._PSS)
If (CondRefOf (\_SB.CP00._PSS)) {
Return (\_SB.CP00._PSS)
} Else {
Return (Package ()
{
@ -155,8 +155,8 @@ Device (B0DB)
/* Check for mainboard specific _PDL override */
If (CondRefOf (\_SB.MPDL)) {
Return (\_SB.MPDL)
} ElseIf (CondRefOf (\_PR.CP00._PSS)) {
Store (SizeOf (\_PR.CP00._PSS ()), Local0)
} ElseIf (CondRefOf (\_SB.CP00._PSS)) {
Store (SizeOf (\_SB.CP00._PSS ()), Local0)
Decrement (Local0)
Return (Local0)
} Else {

4
src/mainboard/roda/rk886ex/acpi/thermal.asl
View file

@ -61,9 +61,9 @@ Scope (\_TZ)
Method (_PSL, 0, Serialized)
{
If (MPEN) {
Return (Package() {\_PR.CP00, \_PR.CP01})
Return (Package() {\_SB.CP00, \_SB.CP01})
}
Return (Package() {\_PR.CP00})
Return (Package() {\_SB.CP00})
}
// TC1 value for passive cooling

4
src/mainboard/roda/rk9/acpi/thermal.asl
View file

@ -79,9 +79,9 @@ Scope (\_TZ)
Method (_PSL, 0, Serialized)
{
If (MPEN) {
Return (Package() {\_PR.CP00, \_PR.CP01})
Return (Package() {\_SB.CP00, \_SB.CP01})
}
Return (Package() {\_PR.CP00})
Return (Package() {\_SB.CP00})
}
// TC1 value for passive cooling

6
src/northbridge/intel/haswell/acpi/hostbridge.asl
View file

@ -151,16 +151,16 @@ Device (MCHC)
* Package (6) { freq, power, tlat, blat, control, status }
* }
*/
External (\_PR.CP00._PSS)
External (\_SB.CP00._PSS)
Method (PSSS, 1, NotSerialized)
{
Store (One, Local0) /* Start at P1 */
Store (SizeOf (\_PR.CP00._PSS), Local1)
Store (SizeOf (\_SB.CP00._PSS), Local1)
While (LLess (Local0, Local1)) {
/* Store _PSS entry Control value to Local2 */
ShiftRight (DeRefOf (Index (DeRefOf (Index
(\_PR.CP00._PSS, Local0)), 4)), 8, Local2)
(\_SB.CP00._PSS, Local0)), 4)), 8, Local2)
If (LEqual (Local2, Arg0)) {
Return (Subtract (Local0, 1))
}

6
src/northbridge/intel/ironlake/acpi/hostbridge.asl
View file

@ -102,16 +102,16 @@ Device (MCHC)
* Package (6) { freq, power, tlat, blat, control, status }
* }
*/
External (\_PR.CP00._PSS)
External (\_SB.CP00._PSS)
Method (PSSS, 1, NotSerialized)
{
Store (One, Local0) /* Start at P1 */
Store (SizeOf (\_PR.CP00._PSS), Local1)
Store (SizeOf (\_SB.CP00._PSS), Local1)
While (LLess (Local0, Local1)) {
/* Store _PSS entry Control value to Local2 */
ShiftRight (DeRefOf (Index (DeRefOf (Index
(\_PR.CP00._PSS, Local0)), 4)), 8, Local2)
(\_SB.CP00._PSS, Local0)), 4)), 8, Local2)
If (LEqual (Local2, Arg0)) {
Return (Subtract (Local0, 1))
}

6
src/northbridge/intel/sandybridge/acpi/hostbridge.asl
View file

@ -141,16 +141,16 @@ Device (MCHC)
* Package (6) { freq, power, tlat, blat, control, status }
* }
*/
External (\_PR.CP00._PSS)
External (\_SB.CP00._PSS)
Method (PSSS, 1, NotSerialized)
{
Store (One, Local0) /* Start at P1 */
Store (SizeOf (\_PR.CP00._PSS), Local1)
Store (SizeOf (\_SB.CP00._PSS), Local1)
While (LLess (Local0, Local1)) {
/* Store _PSS entry Control value to Local2 */
ShiftRight (DeRefOf (Index (DeRefOf (Index
(\_PR.CP00._PSS, Local0)), 4)), 8, Local2)
(\_SB.CP00._PSS, Local0)), 4)), 8, Local2)
If (LEqual (Local2, Arg0)) {
Return (Subtract (Local0, 1))
}

2
src/soc/intel/baytrail/acpi.c
View file

@ -419,7 +419,7 @@ void generate_cpu_entries(struct device *device)
plen = 0;
}
/* Generate processor \_PR.CPUx */
/* Generate processor \_SB.CPUx */
acpigen_write_processor(
core, pcontrol_blk, plen);

38
src/soc/intel/baytrail/acpi/dptf/cpu.asl
View file

@ -12,11 +12,11 @@
* GNU General Public License for more details.
*/
External (\_PR.CP00._TSS, MethodObj)
External (\_PR.CP00._TPC, MethodObj)
External (\_PR.CP00._PTC, PkgObj)
External (\_PR.CP00._TSD, PkgObj)
External (\_PR.CP00._PSS, MethodObj)
External (\_SB.CP00._TSS, MethodObj)
External (\_SB.CP00._TPC, MethodObj)
External (\_SB.CP00._PTC, PkgObj)
External (\_SB.CP00._TSD, PkgObj)
External (\_SB.CP00._PSS, MethodObj)
Device (TCPU)
{
@ -38,8 +38,8 @@ Device (TCPU)
Method (_TSS)
{
If (CondRefOf (\_PR.CP00._TSS)) {
Return (\_PR.CP00._TSS)
If (CondRefOf (\_SB.CP00._TSS)) {
Return (\_SB.CP00._TSS)
} Else {
Return (Package ()
{
@ -50,8 +50,8 @@ Device (TCPU)
Method (_TPC)
{
If (CondRefOf (\_PR.CP00._TPC)) {
Return (\_PR.CP00._TPC)
If (CondRefOf (\_SB.CP00._TPC)) {
Return (\_SB.CP00._TPC)
} Else {
Return (0)
}
@ -59,8 +59,8 @@ Device (TCPU)
Method (_PTC)
{
If (CondRefOf (\_PR.CP00._PTC)) {
Return (\_PR.CP00._PTC)
If (CondRefOf (\_SB.CP00._PTC)) {
Return (\_SB.CP00._PTC)
} Else {
Return (Package ()
{
@ -72,8 +72,8 @@ Device (TCPU)
Method (_TSD)
{
If (CondRefOf (\_PR.CP00._TSD)) {
Return (\_PR.CP00._TSD)
If (CondRefOf (\_SB.CP00._TSD)) {
Return (\_SB.CP00._TSD)
} Else {
Return (Package ()
{
@ -84,8 +84,8 @@ Device (TCPU)
Method (_TDL)
{
If (CondRefOf (\_PR.CP00._TSS)) {
Store (SizeOf (\_PR.CP00._TSS ()), Local0)
If (CondRefOf (\_SB.CP00._TSS)) {
Store (SizeOf (\_SB.CP00._TSS ()), Local0)
Decrement (Local0)
Return (Local0)
} Else {
@ -112,8 +112,8 @@ Device (TCPU)
Method (_PSS)
{
If (CondRefOf (\_PR.CP00._PSS)) {
Return (\_PR.CP00._PSS)
If (CondRefOf (\_SB.CP00._PSS)) {
Return (\_SB.CP00._PSS)
} Else {
Return (Package ()
{
@ -127,8 +127,8 @@ Device (TCPU)
/* Check for mainboard specific _PDL override */
If (CondRefOf (\_SB.MPDL)) {
Return (\_SB.MPDL)
} ElseIf (CondRefOf (\_PR.CP00._PSS)) {
Store (SizeOf (\_PR.CP00._PSS ()), Local0)
} ElseIf (CondRefOf (\_SB.CP00._PSS)) {
Store (SizeOf (\_SB.CP00._PSS ()), Local0)
Decrement (Local0)
Return (Local0)
} Else {

2
src/soc/intel/braswell/acpi.c
View file

@ -422,7 +422,7 @@ void generate_cpu_entries(struct device *device)
plen = 0;
}
/* Generate processor \_PR.CPUx */
/* Generate processor \_SB.CPUx */
acpigen_write_processor(core, pcontrol_blk, plen);
/* Generate P-state tables */

38
src/soc/intel/braswell/acpi/dptf/cpu.asl
View file

@ -41,11 +41,11 @@
#define DPTF_CPU_ACTIVE_AC4 50
#endif
External (\_PR.CP00._TSS, MethodObj)
External (\_PR.CP00._TPC, MethodObj)
External (\_PR.CP00._PTC, PkgObj)
External (\_PR.CP00._TSD, PkgObj)
External (\_PR.CP00._PSS, MethodObj)
External (\_SB.CP00._TSS, MethodObj)
External (\_SB.CP00._TPC, MethodObj)
External (\_SB.CP00._PTC, PkgObj)
External (\_SB.CP00._TSD, PkgObj)
External (\_SB.CP00._PSS, MethodObj)
Device (B0DB)
{
@ -66,8 +66,8 @@ Device (B0DB)
Method (_TSS)
{
If (CondRefOf (\_PR.CP00._TSS)) {
Return (\_PR.CP00._TSS)
If (CondRefOf (\_SB.CP00._TSS)) {
Return (\_SB.CP00._TSS)
} Else {
Return (Package ()
{
@ -78,8 +78,8 @@ Device (B0DB)
Method (_TPC)
{
If (CondRefOf (\_PR.CP00._TPC)) {
Return (\_PR.CP00._TPC)
If (CondRefOf (\_SB.CP00._TPC)) {
Return (\_SB.CP00._TPC)
} Else {
Return (0)
}
@ -87,8 +87,8 @@ Device (B0DB)
Method (_PTC)
{
If (CondRefOf (\_PR.CP00._PTC)) {
Return (\_PR.CP00._PTC)
If (CondRefOf (\_SB.CP00._PTC)) {
Return (\_SB.CP00._PTC)
} Else {
Return (Package ()
{
@ -100,8 +100,8 @@ Device (B0DB)
Method (_TSD)
{
If (CondRefOf (\_PR.CP00._TSD)) {
Return (\_PR.CP00._TSD)
If (CondRefOf (\_SB.CP00._TSD)) {
Return (\_SB.CP00._TSD)
} Else {
Return (Package ()
{
@ -112,8 +112,8 @@ Device (B0DB)
Method (_TDL)
{
If (CondRefOf (\_PR.CP00._TSS)) {
Store (SizeOf (\_PR.CP00._TSS ()), Local0)
If (CondRefOf (\_SB.CP00._TSS)) {
Store (SizeOf (\_SB.CP00._TSS ()), Local0)
Decrement (Local0)
Return (Local0)
} Else {
@ -140,8 +140,8 @@ Device (B0DB)
Method (_PSS)
{
If (CondRefOf (\_PR.CP00._PSS)) {
Return (\_PR.CP00._PSS)
If (CondRefOf (\_SB.CP00._PSS)) {
Return (\_SB.CP00._PSS)
} Else {
Return (Package ()
{
@ -155,8 +155,8 @@ Device (B0DB)
/* Check for mainboard specific _PDL override */
If (CondRefOf (\_SB.MPDL)) {
Return (\_SB.MPDL)
} ElseIf (CondRefOf (\_PR.CP00._PSS)) {
Store (SizeOf (\_PR.CP00._PSS ()), Local0)
} ElseIf (CondRefOf (\_SB.CP00._PSS)) {
Store (SizeOf (\_SB.CP00._PSS ()), Local0)
Decrement (Local0)
Return (Local0)
} Else {

2
src/soc/intel/broadwell/acpi.c
View file

@ -517,7 +517,7 @@ void generate_cpu_entries(struct device *device)
plen = 0;
}
/* Generate processor \_PR.CPUx */
/* Generate processor \_SB.CPUx */
acpigen_write_processor(
(cpuID - 1) * cores_per_package+coreID - 1,
pcontrol_blk, plen);

6
src/soc/intel/broadwell/acpi/ctdp.asl
View file

@ -71,16 +71,16 @@ Scope (\_SB.PCI0.MCHC)
* Package (6) { freq, power, tlat, blat, control, status }
* }
*/
External (\_PR.CP00._PSS)
External (\_SB.CP00._PSS)
Method (PSSS, 1, NotSerialized)
{
Store (One, Local0) /* Start at P1 */
Store (SizeOf (\_PR.CP00._PSS), Local1)
Store (SizeOf (\_SB.CP00._PSS), Local1)
While (LLess (Local0, Local1)) {
/* Store _PSS entry Control value to Local2 */
ShiftRight (DeRefOf (Index (DeRefOf (Index
(\_PR.CP00._PSS, Local0)), 4)), 8, Local2)
(\_SB.CP00._PSS, Local0)), 4)), 8, Local2)
If (LEqual (Local2, Arg0)) {
Return (Subtract (Local0, 1))
}

38
src/soc/intel/common/acpi/dptf/cpu.asl
View file

@ -12,11 +12,11 @@
* GNU General Public License for more details.
*/
External (\_PR.CP00._PSS, PkgObj)
External (\_PR.CP00._TSS, PkgObj)
External (\_PR.CP00._TPC, MethodObj)
External (\_PR.CP00._PTC, PkgObj)
External (\_PR.CP00._TSD, PkgObj)
External (\_SB.CP00._PSS, PkgObj)
External (\_SB.CP00._TSS, PkgObj)
External (\_SB.CP00._TPC, MethodObj)
External (\_SB.CP00._PTC, PkgObj)
External (\_SB.CP00._TSD, PkgObj)
External (\_SB.MPDL, IntObj)
Device (DPTF_CPU_DEVICE)
@ -38,8 +38,8 @@ Device (DPTF_CPU_DEVICE)
Method (_TSS)
{
If (CondRefOf (\_PR.CP00._TSS)) {
Return (\_PR.CP00._TSS)
If (CondRefOf (\_SB.CP00._TSS)) {
Return (\_SB.CP00._TSS)
} Else {
Return (Package ()
{
@ -50,8 +50,8 @@ Device (DPTF_CPU_DEVICE)
Method (_TPC)
{
If (CondRefOf (\_PR.CP00._TPC)) {
Return (\_PR.CP00._TPC)
If (CondRefOf (\_SB.CP00._TPC)) {
Return (\_SB.CP00._TPC)
} Else {
Return (0)
}
@ -59,8 +59,8 @@ Device (DPTF_CPU_DEVICE)
Method (_PTC)
{
If (CondRefOf (\_PR.CP00._PTC)) {
Return (\_PR.CP00._PTC)
If (CondRefOf (\_SB.CP00._PTC)) {
Return (\_SB.CP00._PTC)
} Else {
Return (Package ()
{
@ -72,8 +72,8 @@ Device (DPTF_CPU_DEVICE)
Method (_TSD)
{
If (CondRefOf (\_PR.CP00._TSD)) {
Return (\_PR.CP00._TSD)
If (CondRefOf (\_SB.CP00._TSD)) {
Return (\_SB.CP00._TSD)
} Else {
Return (Package ()
{
@ -84,8 +84,8 @@ Device (DPTF_CPU_DEVICE)
Method (_TDL)
{
If (CondRefOf (\_PR.CP00._TSS)) {
Store (SizeOf (\_PR.CP00._TSS), Local0)
If (CondRefOf (\_SB.CP00._TSS)) {
Store (SizeOf (\_SB.CP00._TSS), Local0)
Decrement (Local0)
Return (Local0)
} Else {
@ -112,8 +112,8 @@ Device (DPTF_CPU_DEVICE)
Method (_PSS)
{
If (CondRefOf (\_PR.CP00._PSS)) {
Return (\_PR.CP00._PSS)
If (CondRefOf (\_SB.CP00._PSS)) {
Return (\_SB.CP00._PSS)
} Else {
Return (Package ()
{
@ -128,8 +128,8 @@ Device (DPTF_CPU_DEVICE)
/* Check for mainboard specific _PDL override */
If (CondRefOf (\_SB.MPDL)) {
Return (\_SB.MPDL)
} ElseIf (CondRefOf (\_PR.CP00._PSS)) {
Store (SizeOf (\_PR.CP00._PSS), Local0)
} ElseIf (CondRefOf (\_SB.CP00._PSS)) {
Store (SizeOf (\_SB.CP00._PSS), Local0)
Decrement (Local0)
Return (Local0)
} Else {

2
src/soc/intel/common/block/acpi/acpi.c
View file

@ -433,7 +433,7 @@ void generate_cpu_entries(struct device *device)
plen = 0;
}
/* Generate processor \_PR.CPUx */
/* Generate processor \_SB.CPUx */
acpigen_write_processor((cpu_id) * cores_per_package +
core_id, pcontrol_blk, plen);

2
src/soc/intel/skylake/acpi.c
View file

@ -522,7 +522,7 @@ void generate_cpu_entries(struct device *device)
plen = 0;
}
/* Generate processor \_PR.CPUx */
/* Generate processor \_SB.CPUx */
acpigen_write_processor(
cpu_id*cores_per_package+core_id,
pcontrol_blk, plen);

10
src/soc/intel/skylake/acpi/dptf/cpu.asl
View file

@ -20,7 +20,7 @@
#define DPTF_CPU_CRITICAL 90
#endif
External (\_PR.CP00._PSS, PkgObj)
External (\_SB.CP00._PSS, PkgObj)
External (\_SB.MPDL, IntObj)
Device (B0D4)
@ -55,8 +55,8 @@ Device (B0D4)
Method (_PSS)
{
If (CondRefOf (\_PR.CP00._PSS)) {
Return (\_PR.CP00._PSS)
If (CondRefOf (\_SB.CP00._PSS)) {
Return (\_SB.CP00._PSS)
} Else {
Return (Package ()
{
@ -71,8 +71,8 @@ Device (B0D4)
/* Check for mainboard specific _PDL override */
If (CondRefOf (\_SB.MPDL)) {
Return (\_SB.MPDL)
} ElseIf (CondRefOf (\_PR.CP00._PSS)) {
Store (SizeOf (\_PR.CP00._PSS), Local0)
} ElseIf (CondRefOf (\_SB.CP00._PSS)) {
Store (SizeOf (\_SB.CP00._PSS), Local0)
Decrement (Local0)
Return (Local0)
} Else {

2
src/southbridge/intel/i82371eb/acpi_tables.c
View file

@ -44,7 +44,7 @@ void generate_cpu_entries(struct device *device)
/* without the outer scope, furhter ssdt addition will end up
* within the processor statement */
acpigen_write_scope("\\_PR");
acpigen_write_scope("\\_SB");
for (cpu=0; cpu < numcpus; cpu++) {
acpigen_write_processor(cpu, pcontrol_blk, plen);
acpigen_pop_len();