From be31c8a212cb72d5689e3d8ffc7894791db0b174 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sun, 1 Feb 2026 10:00:03 +0100 Subject: [PATCH] nb/intel/sandybridge: Advertise all MCH BARs Currently not all fixed MMIO ranges are advertised to the resource allocator. This is not an issue as long bottom-up allocation is used and as long as only small PCI BARs are present on the system. Tell the PCI resource allocator about active MCH BARs to not overlap PCI BARs with MCH BARs. TEST=Can still boot on Lenovo X220. No issues seen in coreboot or Linux. Change-Id: I9148ce492b3b16542bae2737c98b0e6fd0701745 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/91039 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/sandybridge/northbridge.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 998562cbed..0d691d9343 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -201,6 +201,20 @@ static void mc_read_resources(struct device *dev) printk(BIOS_DEBUG, "DPR base 0x%08x size %uM\n", dpr_base_k * KiB, dpr.size); } + /* Non standard BARs */ + u64 bar = pci_read_config32(dev, MCHBAR); + bar |= ((u64)pci_read_config32(dev, MCHBAR + 4) << 32); + if (bar & 1) + mmio_range(dev, index++, bar & ~0xf, 0x8000); + bar = pci_read_config32(dev, DMIBAR); + bar |= ((u64)pci_read_config32(dev, DMIBAR + 4) << 32); + if (bar & 1) + mmio_range(dev, index++, bar & ~0xf, 0x1000); + bar = pci_read_config32(dev, EPBAR); + bar |= ((u64)pci_read_config32(dev, EPBAR + 4) << 32); + if (bar & 1) + mmio_range(dev, index++, bar & ~0xf, 0x1000); + printk(BIOS_INFO, "Available memory below 4GB: %lluM\n", tomk >> 10); /* Report the memory regions */