From be288014cc59b14dae292b5d26c9ff320955d83e Mon Sep 17 00:00:00 2001 From: Barnali Sarkar Date: Fri, 3 Feb 2017 13:28:46 +0530 Subject: [PATCH] UPSTREAM: vendorcode/intel/skykabylake: Update CpuConfigFspData.h file The FSP UPD offsets and the corresponding structure size do not match, CpuConfigData.h needs an update to align the same. Hence update the header file based on FSP version 1.4.0. BUG=chrome-os-partner:61548 BRANCH=none TEST=Built and booted KBLRVP and verify that all UPDs are in sync in both coreboot and FSP. Change-Id: I817c13aaac891f5aef075ba66d8d66aba2346f97 Signed-off-by: Patrick Georgi Original-Commit-Id: 6ff7e8f550df1ef05e93546892888b66c132ae31 Original-Change-Id: I5ef7cbb569c3d1a44e7846717201952a0acf12ab Original-Signed-off-by: Barnali Sarkar Original-Reviewed-on: https://review.coreboot.org/18285 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Subrata Banik Original-Reviewed-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/440166 --- .../fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h index 8fd41e07d7..c8cdc5fd27 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h @@ -62,9 +62,9 @@ typedef union { UINT32 TxtEnable : 1; UINT32 SkipMpInit : 1; ///< For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0. UINT32 RsvdBits : 15; ///< Reserved for future use - EFI_PHYSICAL_ADDRESS MicrocodePatchAddress; ///< Pointer to microcode patch that is suitable for this processor. + UINT32 Reserved; } Bits; - UINT32 Uint32[3]; + UINT32 Uint32[2]; } CPU_CONFIG_FSP_DATA; #pragma pack (pop)