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haswell: configure c-states

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The c-states are configured according to the BWG, however the
package c-states are disabled as they currently cause platform
instability. The exposed ACPI c-state to processor c-state mapping
are as follows for ULT boards:
	ACPI(C1) = MWAIT(C1E)
	ACPI(C2) = MWAIT(C7S long latency)
	ACPI(C3) = MWAIT(C10)
The non-ULT boards have an expoed c-state mapping:
	ACPI(C1) = MWAIT(C1E)
	ACPI(C2) = MWAIT(C3)
	ACPI(C3) = MWAIT(C7S)

Included in this patch is removing the updating of current limit
registers as some of the MSRs are different and the proper values
are currently unknown. Lastly, some of the MSRs were renamed to
match the BWG.

BUG=None
BRANCH=None
TEST=Booted 3.8 kernel and used powertop to note package, core, and acpi
     c-state residency.

Change-Id: Ia428d4a4979ba3cba44eb9faa96f74b7d3f22dfe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48291
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
This commit is contained in:
Aaron Durbin 2013-04-10 14:46:25 -05:00 • committed by ChromeBot
commit bde97c09ad
5 changed files with 174 additions and 125 deletions
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12
src/mainboard/intel/baskingridge/devicetree.cb
View file

@ -17,13 +17,13 @@ chip northbridge/intel/haswell
# Magic APIC ID to locate this chip
device lapic 0xACAC off end
register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3)
register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6)
register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E)
register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S)
register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3)
register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6)
register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E)
register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S)
end
end

12
src/mainboard/intel/wtm1/devicetree.cb
View file

@ -17,13 +17,13 @@ chip northbridge/intel/haswell
# Magic APIC ID to locate this chip
device lapic 0xACAC off end
register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3)
register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6)
register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E)
register "c2_battery" = "9" # ACPI(C2) = MWAIT(C7S)
register "c3_battery" = "12" # ACPI(C3) = MWAIT(C10)
register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3)
register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6)
register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E)
register "c2_acpower" = "9" # ACPI(C2) = MWAIT(C7S)
register "c3_acpower" = "12" # ACPI(C3) = MWAIT(C10)
end
end

12
src/mainboard/intel/wtm2/devicetree.cb
View file

@ -17,13 +17,13 @@ chip northbridge/intel/haswell
# Magic APIC ID to locate this chip
device lapic 0xACAC off end
register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3)
register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6)
register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E)
register "c2_battery" = "9" # ACPI(C2) = MWAIT(C7S)
register "c3_battery" = "12" # ACPI(C3) = MWAIT(C10)
register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3)
register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6)
register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E)
register "c2_acpower" = "9" # ACPI(C2) = MWAIT(C7S)
register "c3_acpower" = "12" # ACPI(C3) = MWAIT(C10)
end
end