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This patch fixes up k8 for the new resource allocator. It splits

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northbridge functions and makes devices children of the northbridge.
	
northbridge/amd/k8/domain.c: 
	Add the functions from k8/pci.c that belong to the domain.  Add
support for physical link numbers in resource indices.  Combine find_iopair
and find_mempair to find_regpair.

northbridge/amd/k8/pci.c:
	Remove functions that went to the domain.

device/hypertransport.c:
	Add support for HT connections from devices that aren't the bus
controller.

device/hypertransport.h:
	Change the prototype of hypertransport_scan_chain.

northbridge/amd/k8/pci:
	Take out bridge flag.

mainboard/amd/serengeti/stage1.c
	Change first register usage.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1094 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Myles Watson 2009-01-05 16:00:32 +00:00
commit bdc76a22a0
6 changed files with 538 additions and 699 deletions
Download patch file Download diff file Expand all files Collapse all files

26
device/hypertransport.c
View file

@ -287,15 +287,15 @@ static unsigned int ht_lookup_slave_capability(struct device *dev)
return pos;
}
static void ht_collapse_early_enumeration(struct bus *bus,
static void ht_collapse_early_enumeration(struct bus *bus, struct device* htdev,
unsigned int offset_unitid)
{
unsigned int devfn, ctrl;
struct ht_link prev;
/* Initialize the hypertransport enumeration state. */
prev.dev = bus->dev;
prev.pos = bus->cap;
prev.dev = htdev;
prev.pos = htdev->link[0].cap;
prev.ctrl_off = PCI_HT_CAP_HOST_CTRL;
prev.config_off = PCI_HT_CAP_HOST_WIDTH;
prev.freq_off = PCI_HT_CAP_HOST_FREQ;
@ -384,7 +384,8 @@ static void ht_collapse_early_enumeration(struct bus *bus,
}
}
unsigned int hypertransport_scan_chain(struct bus *bus, unsigned int min_devfn,
unsigned int hypertransport_scan_chain(struct device* htdev, struct bus *bus,
unsigned int min_devfn,
unsigned int max_devfn,
unsigned int max,
unsigned int *ht_unitid_base,
@ -411,15 +412,15 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned int min_devfn,
#endif
/* Restore the hypertransport chain to its unitialized state. */
ht_collapse_early_enumeration(bus, offset_unitid);
ht_collapse_early_enumeration(bus, htdev, offset_unitid);
/* See which static device nodes I have. */
old_devices = bus->children;
bus->children = 0;
bus->children = NULL;
/* Initialize the hypertransport enumeration state. */
prev.dev = bus->dev;
prev.pos = bus->cap;
prev.dev = htdev;
prev.pos = htdev->link[0].cap;
prev.ctrl_off = PCI_HT_CAP_HOST_CTRL;
prev.config_off = PCI_HT_CAP_HOST_WIDTH;
prev.freq_off = PCI_HT_CAP_HOST_FREQ;
@ -525,7 +526,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned int min_devfn,
next_unitid += count;
/* Setup the hypertransport link. */
bus->reset_needed |= ht_setup_link(&prev, dev, pos);
htdev->link[0].reset_needed |= ht_setup_link(&prev, dev, pos);
printk(BIOS_DEBUG, "%s [%04x/%04x] %s next_unitid: %04x\n",
dev_path(dev),
@ -537,7 +538,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned int min_devfn,
&& (next_unitid <= (max_devfn >> 3)));
end_of_chain:
#if OPT_HT_LINK == 1
if (bus->reset_needed) {
if (htdev->link[0].reset_needed) {
printk(BIOS_INFO, "HyperT reset needed\n");
} else {
printk(BIOS_DEBUG, "HyperT reset not needed\n");
@ -621,8 +622,9 @@ unsigned int hypertransport_scan_chain_x(struct bus *bus,
{
unsigned int ht_unitid_base[4];
unsigned int offset_unitid = 1;
return hypertransport_scan_chain(bus, min_devfn, max_devfn, max,
ht_unitid_base, offset_unitid);
return hypertransport_scan_chain(bus->dev, bus, min_devfn,
max_devfn, max, ht_unitid_base,
offset_unitid);
}
unsigned int ht_scan_bridge(struct device *dev, unsigned int max)

6
include/device/hypertransport.h
View file

@ -21,8 +21,10 @@
#include <device/device.h>
#include <device/hypertransport_def.h>
unsigned int hypertransport_scan_chain(struct bus *bus,
unsigned min_devfn, unsigned max_devfn, unsigned int max, unsigned *ht_unit_base, unsigned offset_unitid);
unsigned int hypertransport_scan_chain(struct device* parent, struct bus *bus,
unsigned min_devfn, unsigned max_devfn,
unsigned int max, unsigned *ht_unit_base,
unsigned offset_unitid);
unsigned int ht_scan_bridge(struct device *dev, unsigned int max);
extern const struct device_operations default_ht_ops_bus;

8
mainboard/amd/serengeti/stage1.c
View file

@ -210,10 +210,10 @@ static const struct rmap register_values[] = {
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
PCM(0, 0x18, 1, 0xC4, 0xFE000FC8, 0x01fff000),
PCM(0, 0x18, 1, 0xC4, 0xFE000FC8, 0x00000000),
PCM(0, 0x18, 1, 0xCC, 0xFE000FC8, 0x00000000),
PCM(0, 0x18, 1, 0xD4, 0xFE000FC8, 0x00000000),
PCM(0, 0x18, 1, 0xDC, 0xFE000FC8, 0x00000000),
PCM(0, 0x18, 1, 0xDC, 0xFE000FC8, 0x01fff000),
/* PCI I/O Base i Registers
* F1:0xC0 i = 0
@ -240,10 +240,10 @@ static const struct rmap register_values[] = {
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
PCM(0, 0x18, 1, 0xC0, 0xFE000FCC, 0x00000003),
PCM(0, 0x18, 1, 0xC0, 0xFE000FCC, 0x00000000),
PCM(0, 0x18, 1, 0xC8, 0xFE000FCC, 0x00000000),
PCM(0, 0x18, 1, 0xD0, 0xFE000FCC, 0x00000000),
PCM(0, 0x18, 1, 0xD8, 0xFE000FCC, 0x00000000),
PCM(0, 0x18, 1, 0xD8, 0xFE000FCC, 0x00000003),
/* Config Base and Limit i Registers
* F1:0xE0 i = 0

648
northbridge/amd/k8/domain.c
View file

@ -7,6 +7,7 @@
* Copyright (C) 2005 Ollie Lo
* Copyright (C) 2005-2007 Stefan Reinauer <stepan@openbios.org>
* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
* Copyright (C) 2008-2009 Myles Watson <mylesgw@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -46,27 +47,18 @@
#include <lib.h>
#include <lapic.h>
#define K8_RESOURCE_INDEX(node, func, link, reg) (((node) << 16) | ((func<<8) | (reg) | (link)))
#define K8_RESOURCE_NODE(index) (((index) & 0x70000)>>16)
#define K8_RESOURCE_REG(index) ((index) & 0xfc)
#define K8_RESOURCE_LINK(index) ((index) & 0x3)
#define K8_RESOURCE_FUNC(index) (((index) & 0x700)>>8)
#define FX_DEVS 8
extern struct device * __f0_dev[FX_DEVS];
u32 f1_read_config32(unsigned int reg);
void f1_write_config32(unsigned int reg, u32 value);
unsigned int amdk8_nodeid(struct device * dev);
static void k8_ram_resource(struct device * dev, unsigned long index,
unsigned long basek, unsigned long sizek)
{
struct resource *resource;
if (!sizek) {
return;
}
resource = new_resource(dev, index);
resource->base = ((resource_t)basek) << 10;
resource->size = ((resource_t)sizek) << 10;
resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
static void tolm_test(void *gp, struct device *dev, struct resource *new)
{
struct resource **best_p = gp;
@ -91,68 +83,306 @@ static u32 find_pci_tolm(struct bus *bus)
return tolm;
}
static void k8_pci_domain_read_resources(struct device * dev)
/**
* reg_useable
* @param reg register to check
* @param goal_dev device to own the resource
* @param goal_nodeid node number
* @param goal_link link number
* @return 0 if not useable, 1 if useable, or 2 if the pair is free
*/
static int reg_useable(unsigned reg, struct device *dev, unsigned goal_nodeid,
unsigned goal_link)
{
struct resource *resource;
unsigned reg;
struct resource *res = NULL;
unsigned nodeid = 0, link = 0;
int result;
/* Find the already assigned resource pairs */
printk(BIOS_DEBUG, "k8_pci_domain_read_resources\n");
for(reg = 0x80; reg <= 0xd8; reg+= 0x08) {
u32 base, limit;
base = f1_read_config32(reg);
limit = f1_read_config32(reg + 0x04);
/* Is this register allocated? */
if ((base & 3) != 0) {
unsigned nodeid, link;
struct device * dev;
nodeid = limit & 7;
link = (limit >> 4) & 3;
dev = __f0_dev[nodeid]; /* Initialized by f1_read_config32. */
if (dev) {
/* Reserve the resource */
struct resource *resource;
resource = new_resource(dev, 0x100 + (reg | link));
if (resource) {
resource->flags = 1;
}
}
/* Look for the resource that matches this register. */
for(nodeid = 0; !res && (nodeid < FX_DEVS); nodeid++) {
for (link = 0; !res && (link < 3); link++) {
res = probe_resource(dev,K8_RESOURCE_INDEX(nodeid,1,link,reg));
}
}
#ifndef CONFIG_PCI_64BIT_PREF_MEM
/* Initialize the system-wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
resource->base = 0x400;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system-wide memory resource constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
#else
/* Initialize the system-wide io space constraints */
resource = new_resource(dev, 0);
resource->base = 0x400;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
if (res) {
/* If the resource is allocated to the link and node already. */
if (0 && (goal_link == K8_RESOURCE_LINK(res->index)) &&
(goal_nodeid == K8_RESOURCE_NODE(res->index)) &&
(res->flags <= 1)) {
printk(BIOS_DEBUG, "Re-allocated resource %lx!\n",
res->index);
result = 1;
}
/* Allocated, but not to this node. */
else
result = 0;
} else
/* If no allocated resource was found, it is free - return 2. */
result = 2;
/* Initialize the system-wide prefetchable memory resource constraints */
resource = new_resource(dev, 1);
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
return result;
}
/* Initialize the system-wide memory resource constraints */
resource = new_resource(dev, 2);
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM;
static struct resource *amdk8_find_regpair(struct device *dev, unsigned nodeid,
unsigned minreg, unsigned maxreg,
unsigned link)
{
struct resource *resource;
unsigned free_reg, reg;
resource = NULL;
free_reg = 0;
for (reg = minreg; reg <= maxreg; reg += 0x8) {
int result;
result = reg_useable(reg, dev, nodeid, link);
if (result == 1) {
/* I have been allocated this one */
break;
} else if (result > 1) {
/* I have a free register pair */
free_reg = reg;
}
}
if (reg > maxreg) {
reg = free_reg;
}
if (reg > 0) {
resource = new_resource(dev, 0x100 + (reg | link));
}
return resource;
}
static struct resource *amdk8_find_iopair(struct device *dev, unsigned nodeid,
unsigned link)
{
return amdk8_find_regpair(dev,nodeid,0xc0, 0xd8,link);
}
static struct resource *amdk8_find_mempair(struct device *dev, unsigned nodeid,
unsigned link)
{
return amdk8_find_regpair(dev,nodeid,0x80, 0xb8,link);
}
static void amdk8_link_read_bases(struct device *dev, unsigned nodeid,
unsigned link)
{
struct resource *resource;
/* Initialize the io space constraints on the current bus */
resource = amdk8_find_iopair(dev, nodeid, link);
if (resource) {
resource->base = 0;
resource->size = 0;
resource->align = log2c(HT_IO_HOST_ALIGN);
resource->gran = log2c(HT_IO_HOST_ALIGN);
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
}
/* Initialize the prefetchable memory constraints on the current bus */
resource = amdk8_find_mempair(dev, nodeid, link);
if (resource) {
resource->base = 0;
resource->size = 0;
resource->align = log2c(HT_MEM_HOST_ALIGN);
resource->gran = log2c(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
#ifdef CONFIG_PCI_64BIT_PREF_MEM
resource->flags |= IORESOURCE_BRIDGE;
#endif
printk(BIOS_DEBUG, "k8_pci_domain_read_resources done\n");
}
/* Initialize the memory constraints on the current bus */
resource = amdk8_find_mempair(dev, nodeid, link);
if (resource) {
resource->base = 0;
resource->size = 0;
resource->align = log2c(HT_MEM_HOST_ALIGN);
resource->gran = log2c(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
}
}
static void k8_pci_domain_read_resources(struct device *dev)
{
printk(BIOS_DEBUG, "%s\n", __func__);
unsigned link;
for (link = 0; link < dev->links; link++) {
if (dev->link[link].children) {
amdk8_link_read_bases(dev, 0, link);
}
}
printk(BIOS_DEBUG, "%s done\n", __func__);
}
static void amdk8_set_resource(struct device *dev, struct resource *resource)
{
resource_t rbase, rend;
unsigned reg, link, nodeid, func;
char buf[50];
printk(BIOS_DEBUG, "%s: %s@%lx flags %lx\n", __func__, dev->dtsname,
resource->index, resource->flags);
/* Make certain the resource has actually been set. */
if (!(resource->flags & IORESOURCE_ASSIGNED)) {
return;
}
/* If I have already stored this resource don't worry about it. */
if (resource->flags & IORESOURCE_STORED) {
return;
}
/* Only handle PCI memory and IO resources. */
if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
return;
/* Get the base address. */
rbase = resource->base;
/* Get the limit (rounded up). */
rend = resource_end(resource);
/* Get the register, nodeid, and link */
nodeid = K8_RESOURCE_NODE(resource->index);
reg = K8_RESOURCE_REG(resource->index);
link = K8_RESOURCE_LINK(resource->index);
func = K8_RESOURCE_FUNC(resource->index);
if (func != 1) {
printk(BIOS_INFO, "%s: K8 function %d register!\n", __func__,
func);
return;
}
if (resource->flags & IORESOURCE_IO) {
u32 base, limit;
base = f1_read_config32(reg);
limit = f1_read_config32(reg + 0x4);
base &= 0xfe000fcc;
base |= rbase & 0x01fff000;
base |= 3;
limit &= 0xfe000fc8;
limit |= rend & 0x01fff000;
limit |= (link & 3) << 4;
limit |= (nodeid & 7);
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
printk(BIOS_SPEW,
"%s, enabling legacy VGA IO forwarding for %s link %x\n",
__func__, dev_path(dev), link);
base |= PCI_IO_BASE_VGA_EN;
}
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
base |= PCI_IO_BASE_NO_ISA;
}
f1_write_config32(reg + 0x4, limit);
f1_write_config32(reg, base);
} else if (resource->flags & IORESOURCE_MEM) {
u32 base, limit;
base = f1_read_config32(reg);
limit = f1_read_config32(reg + 0x4);
base &= 0x000000f0;
base |= (rbase >> 8) & 0xffffff00;
base |= 3;
limit &= 0x00000048;
limit |= (rend >> 8) & 0xffffff00;
limit |= (link & 3) << 4;
limit |= (nodeid & 7);
f1_write_config32(reg + 0x4, limit);
f1_write_config32(reg, base);
}
resource->flags |= IORESOURCE_STORED;
sprintf(buf, " <node %d link %d>", nodeid, link);
report_resource_stored(dev, resource, buf);
}
#ifdef CONFIG_MULTIPLE_VGA_INIT
extern struct device *vga_pri; // the primary vga device, defined in device.c
#endif
static void amdk8_create_vga_resource(struct device *dev)
{
struct resource *resource;
unsigned link;
/* find out which link the VGA card is connected,
* we only deal with the 'first' vga card */
for (link = 0; link < dev->links; link++) {
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
#ifdef CONFIG_MULTIPLE_VGA_INIT
printk(BIOS_DEBUG,
"VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n",
vga_pri->bus->secondary,
dev->link[link].secondary,
dev->link[link].subordinate);
/* We need to make sure the vga_pri is under the link */
if ((vga_pri->bus->secondary >=
dev->link[link].secondary)
&& (vga_pri->bus->secondary <=
dev->link[link].subordinate)
)
#endif
break;
}
}
/* no VGA card installed */
if (link == dev->links)
return;
printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n",
dev_path(dev), 0, link);
/* Allocate a resrouce for the legacy VGA buffer. */
resource = amdk8_find_mempair(dev, 0, link);
if (!resource) {
printk(BIOS_DEBUG,
"VGA: Can not find free mmio reg for legacy VGA buffer\n");
return;
}
resource->base = 0xa0000;
resource->size = 0x20000;
resource->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
}
static void amdk8_set_resources(struct device *dev)
{
unsigned link;
int i;
printk(BIOS_DEBUG, "%s\n", __func__);
printk(BIOS_DEBUG, "%s ops %p ops_pci_bus %p\n",
dev->dtsname, dev->ops, dev->ops->ops_pci_bus);
pci_check_pci_ops(dev->ops->ops_pci_bus);
amdk8_create_vga_resource(dev);
/* Set each resource we have found */
for (i = 0; i < dev->resources; i++) {
amdk8_set_resource(dev, &dev->resource[i]);
}
for (link = 0; link < dev->links; link++) {
struct bus *bus;
bus = &dev->link[link];
if (bus->children) {
phase4_set_resources(bus);
}
}
}
static void k8_pci_domain_set_resources(struct device * dev)
{
printk(BIOS_DEBUG, "k8_pci_domain_set_resources\n");
printk(BIOS_DEBUG, "%s\n", __func__);
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info get_hw_mem_hole_info(void);
void disable_hoist_memory(unsigned long hole_startk, int i);
@ -170,69 +400,6 @@ static void k8_pci_domain_set_resources(struct device * dev)
unsigned reset_memhole = 1;
#endif
#if 0
/* Place the IO devices somewhere safe */
io = find_resource(dev, 0);
io->base = DEVICE_IO_START;
#endif
#ifdef CONFIG_PCI_64BIT_PREF_MEM
/* Now reallocate the pci resources memory with the
* highest addresses I can manage.
*/
mem1 = find_resource(dev, 1);
mem2 = find_resource(dev, 2);
#if 1
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
#endif
/* See if both resources have roughly the same limits */
if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
{
/* If so place the one with the most stringent alignment first
*/
if (mem2->align > mem1->align) {
struct resource *tmp;
tmp = mem1;
mem1 = mem2;
mem2 = tmp;
}
/* Now place the memory as high up as it will go */
mem2->base = resource_max(mem2);
mem1->limit = mem2->base - 1;
mem1->base = resource_max(mem1);
}
else {
/* Place the resources as high up as they will go */
mem2->base = resource_max(mem2);
mem1->base = resource_max(mem1);
}
#if 1
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
#endif
last = &dev->resource[dev->resources];
for(resource = &dev->resource[0]; resource < last; resource++)
{
#if 1
resource->flags |= IORESOURCE_ASSIGNED;
resource->flags &= ~IORESOURCE_STORED;
#endif
resource->flags |= IORESOURCE_STORED;
report_resource_stored(dev, resource, "");
}
#endif
pci_tolm = find_pci_tolm(&dev->link[0]);
#warning "FIXME handle interleaved nodes"
@ -240,11 +407,9 @@ static void k8_pci_domain_set_resources(struct device * dev)
/* Round mmio_basek to something the processor can support */
mmio_basek &= ~((1 << 6) -1);
#if 1
#warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole"
/* Round the mmio hole to 64M */
mmio_basek &= ~((64*1024) - 1);
#endif
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
/* If the hw mem hole is already set in raminit stage, here we will
@ -307,7 +472,7 @@ static void k8_pci_domain_set_resources(struct device * dev)
/* see if we need a hole from 0xa0000 to 0xbffff */
if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) {
k8_ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek);
ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek);
idx += 0x10;
basek = (8*64)+(16*16);
sizek = limitk - ((8*64)+(16*16));
@ -323,7 +488,7 @@ static void k8_pci_domain_set_resources(struct device * dev)
unsigned pre_sizek;
pre_sizek = mmio_basek - basek;
if(pre_sizek>0) {
k8_ram_resource(dev, (idx | i), basek, pre_sizek);
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
}
@ -342,22 +507,223 @@ static void k8_pci_domain_set_resources(struct device * dev)
sizek -= (4*1024*1024 - mmio_basek);
}
}
k8_ram_resource(dev, (idx | i), basek, sizek);
ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
}
amdk8_set_resources(dev);
phase4_set_resources(&dev->link[0]);
}
static unsigned int amdk8_scan_chain(struct device *domain,
struct device* k8dev,
unsigned link, unsigned sblink,
unsigned int max, unsigned offset_unitid)
{
u32 link_type;
int i;
u32 busses, config_busses;
unsigned free_reg, config_reg;
unsigned ht_unitid_base[4]; // here assume only 4 HT device on chain
unsigned max_bus;
unsigned min_bus;
unsigned max_devfn;
unsigned nodeid = amdk8_nodeid(k8dev);
printk(BIOS_SPEW, "%s node %x link %x\n", __func__, nodeid, link);
k8dev->link[link].cap = 0x80 + (link * 0x20);
do {
link_type = pci_read_config32(k8dev, k8dev->link[link].cap + 0x18);
} while (link_type & ConnectionPending);
if (!(link_type & LinkConnected)) {
return max;
}
printk(BIOS_DEBUG, "amdk8_scan_chain: link %d is connected\n", link);
do {
link_type = pci_read_config32(k8dev, k8dev->link[link].cap + 0x18);
} while (!(link_type & InitComplete));
if (!(link_type & NonCoherent)) {
return max;
}
/* See if there is an available configuration space mapping
* register in function 1.
*/
free_reg = 0;
for (config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
u32 config;
config = f1_read_config32(config_reg);
if (!free_reg && ((config & 3) == 0)) {
free_reg = config_reg;
continue;
}
if (((config & 3) == 3) &&
(((config >> 4) & 7) == nodeid) &&
(((config >> 8) & 3) == link)) {
break;
}
}
if (free_reg && (config_reg > 0xec)) {
config_reg = free_reg;
}
/* If we can't find an available configuration space mapping
* register skip this bus
*/
if (config_reg > 0xec) {
return max;
}
/* Set up the primary, secondary and subordinate bus numbers.
* We have no idea how many busses are behind this bridge yet,
* so we set the subordinate bus number to 0xff for the moment.
*/
#if SB_HT_CHAIN_ON_BUS0 > 0
// first chain will on bus 0
if ((nodeid == 0) && (sblink == link)) { // actually max is 0 here
min_bus = max;
}
#if SB_HT_CHAIN_ON_BUS0 > 1
// second chain will be on 0x40, third 0x80, forth 0xc0
else {
min_bus = ((max >> 6) + 1) * 0x40;
}
max = min_bus;
#else
//other ...
else {
min_bus = ++max;
}
#endif
#else
min_bus = ++max;
#endif
max_bus = 0xff;
k8dev->link[link].secondary = min_bus;
k8dev->link[link].subordinate = max_bus;
/* Read the existing primary/secondary/subordinate bus
* number configuration.
*/
busses = pci_read_config32(k8dev, k8dev->link[link].cap + 0x14);
config_busses = f1_read_config32(config_reg);
/* Configure the bus numbers for this bridge: the configuration
* transactions will not be propagates by the bridge if it is
* not correctly configured
*/
busses &= 0xff000000;
busses |= (((unsigned int)(k8dev->bus->secondary) << 0) |
((unsigned int)(k8dev->link[link].secondary) << 8) |
((unsigned int)(k8dev->link[link].subordinate) << 16));
pci_write_config32(k8dev, k8dev->link[link].cap + 0x14, busses);
config_busses &= 0x000fc88;
config_busses |= (3 << 0) | /* rw enable, no device compare */
((nodeid & 7) << 4) |
((link & 3) << 8) |
((k8dev->link[link].secondary) << 16) |
((k8dev->link[link].subordinate) << 24);
f1_write_config32(config_reg, config_busses);
/* Now we can scan all of the subordinate busses i.e. the
* chain on the hypertranport link
*/
for (i = 0; i < 4; i++) {
ht_unitid_base[i] = 0x20;
}
max_devfn = PCI_DEVFN(0x1f, 7);
max = hypertransport_scan_chain(k8dev, &domain->link[link], 0,
max_devfn, max, ht_unitid_base,
offset_unitid);
/* We know the number of busses behind this bridge. Set the
* subordinate bus number to it's real value
*/
k8dev->link[link].subordinate = max;
busses = (busses & 0xff00ffff) |
((unsigned int)(k8dev->link[link].subordinate) << 16);
pci_write_config32(k8dev, k8dev->link[link].cap + 0x14, busses);
config_busses = (config_busses & 0x00ffffff) |
(k8dev->link[link].subordinate << 24);
f1_write_config32(config_reg, config_busses);
{
// config config_reg, and ht_unitid_base to update hcdn_reg;
int index;
unsigned temp = 0;
index = (config_reg - 0xe0) >> 2;
for (i = 0; i < 4; i++) {
temp |= (ht_unitid_base[i] & 0xff) << (i * 8);
}
sysconf.hcdn_reg[index] = temp;
}
printk(BIOS_SPEW, "amdk8_scan_chain done\n");
return max;
}
static unsigned int amdk8_scan_chains(struct device *domain, struct device *k8dev,
unsigned int max)
{
unsigned nodeid;
unsigned link;
unsigned sblink = 0;
unsigned offset_unitid = 0;
nodeid = amdk8_nodeid(k8dev);
printk(BIOS_DEBUG, "amdk8_scan_chains\n");
if (nodeid == 0) {
sblink = (pci_read_config32(k8dev, 0x64) >> 8) & 3;
#if SB_HT_CHAIN_ON_BUS0 > 0
#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
offset_unitid = 1;
#endif
// do southbridge ht chain first, in case s2885 put southbridge chain (8131/8111) on link2,
// but put 8151 on link0
max =
amdk8_scan_chain(domain, k8dev, sblink, sblink, max,
offset_unitid);
#endif
}
for (link = 0; link < k8dev->links; link++) {
#if SB_HT_CHAIN_ON_BUS0 > 0
if ((nodeid == 0) && (sblink == link))
continue; //already done
#endif
offset_unitid = 0;
#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
if ((nodeid == 0) && (sblink == link))
#endif
offset_unitid = 1;
#endif
max = amdk8_scan_chain(domain, k8dev, link, sblink, max,
offset_unitid);
}
return max;
}
static unsigned int k8_domain_scan_bus(struct device * dev, unsigned int max)
{
unsigned reg;
int i;
printk(BIOS_DEBUG, "k8_domain_scan_bus\n");
printk(BIOS_DEBUG, "%s: %s \n", __func__, dev->dtsname);
/* Unmap all of the HT chains */
for(reg = 0xe0; reg <= 0xec; reg += 4) {
f1_write_config32(reg, 0);
}
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max);
/* Tune the hypertransport transaction for best performance.
* Including enabling relaxed ordering if it is safe.
@ -379,9 +745,18 @@ static unsigned int k8_domain_scan_bus(struct device * dev, unsigned int max)
pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc);
}
}
max = amdk8_scan_chains(dev, __f0_dev[0], max);
return max;
}
static void k8_pci_domain_enable_resources(struct device *dev)
{
printk(BIOS_DEBUG, "%s\n", __func__);
enable_childrens_resources(dev);
}
struct device_operations k8domain_ops = {
.id = {.type = DEVICE_ID_APIC_CLUSTER,
{.pci_domain = {.vendor = PCI_VENDOR_ID_AMD,
@ -390,7 +765,6 @@ struct device_operations k8domain_ops = {
.phase3_scan = k8_domain_scan_bus,
.phase4_read_resources = k8_pci_domain_read_resources,
.phase4_set_resources = k8_pci_domain_set_resources,
.phase5_enable_resources = enable_childrens_resources,
.ops_pci = &pci_dev_ops_pci,
.phase5_enable_resources = k8_pci_domain_enable_resources,
.ops_pci_bus = &pci_cf8_conf1,
};

1
northbridge/amd/k8/pci
View file

@ -20,5 +20,4 @@
{
device_operations = "k8_ops";
bridge;
};

546
northbridge/amd/k8/pci.c
View file

@ -46,538 +46,6 @@
#include <lib.h>
#include <lapic.h>
u32 f1_read_config32(unsigned int reg);
void f1_write_config32(unsigned int reg, u32 value);
unsigned int amdk8_nodeid(struct device *dev);
static unsigned int amdk8_scan_chain(struct device *dev, unsigned nodeid,
unsigned link, unsigned sblink,
unsigned int max, unsigned offset_unitid)
{
u32 link_type;
int i;
u32 busses, config_busses;
unsigned free_reg, config_reg;
unsigned ht_unitid_base[4]; // here assume only 4 HT device on chain
unsigned max_bus;
unsigned min_bus;
unsigned max_devfn;
printk(BIOS_SPEW, "amdk8_scan_chain link %x\n", link);
dev->link[link].cap = 0x80 + (link * 0x20);
do {
link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
} while (link_type & ConnectionPending);
if (!(link_type & LinkConnected)) {
return max;
}
printk(BIOS_DEBUG, "amdk8_scan_chain: link %d is connected\n", link);
do {
link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
} while (!(link_type & InitComplete));
if (!(link_type & NonCoherent)) {
return max;
}
/* See if there is an available configuration space mapping
* register in function 1.
*/
free_reg = 0;
for (config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
u32 config;
config = f1_read_config32(config_reg);
if (!free_reg && ((config & 3) == 0)) {
free_reg = config_reg;
continue;
}
if (((config & 3) == 3) &&
(((config >> 4) & 7) == nodeid) &&
(((config >> 8) & 3) == link)) {
break;
}
}
if (free_reg && (config_reg > 0xec)) {
config_reg = free_reg;
}
/* If we can't find an available configuration space mapping
* register skip this bus
*/
if (config_reg > 0xec) {
return max;
}
/* Set up the primary, secondary and subordinate bus numbers.
* We have no idea how many busses are behind this bridge yet,
* so we set the subordinate bus number to 0xff for the moment.
*/
#if SB_HT_CHAIN_ON_BUS0 > 0
// first chain will on bus 0
if ((nodeid == 0) && (sblink == link)) { // actually max is 0 here
min_bus = max;
}
#if SB_HT_CHAIN_ON_BUS0 > 1
// second chain will be on 0x40, third 0x80, forth 0xc0
else {
min_bus = ((max >> 6) + 1) * 0x40;
}
max = min_bus;
#else
//other ...
else {
min_bus = ++max;
}
#endif
#else
min_bus = ++max;
#endif
max_bus = 0xff;
dev->link[link].secondary = min_bus;
dev->link[link].subordinate = max_bus;
/* Read the existing primary/secondary/subordinate bus
* number configuration.
*/
busses = pci_read_config32(dev, dev->link[link].cap + 0x14);
config_busses = f1_read_config32(config_reg);
/* Configure the bus numbers for this bridge: the configuration
* transactions will not be propagates by the bridge if it is
* not correctly configured
*/
busses &= 0xff000000;
busses |= (((unsigned int)(dev->bus->secondary) << 0) |
((unsigned int)(dev->link[link].secondary) << 8) |
((unsigned int)(dev->link[link].subordinate) << 16));
pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
config_busses &= 0x000fc88;
config_busses |= (3 << 0) | /* rw enable, no device compare */
((nodeid & 7) << 4) |
((link & 3) << 8) |
((dev->link[link].secondary) << 16) |
((dev->link[link].subordinate) << 24);
f1_write_config32(config_reg, config_busses);
/* Now we can scan all of the subordinate busses i.e. the
* chain on the hypertranport link
*/
for (i = 0; i < 4; i++) {
ht_unitid_base[i] = 0x20;
}
if (min_bus == 0)
max_devfn = (0x17 << 3) | 7;
else
max_devfn = (0x1f << 3) | 7;
max =
hypertransport_scan_chain(&dev->link[link], 0, max_devfn, max,
ht_unitid_base, offset_unitid);
/* We know the number of busses behind this bridge. Set the
* subordinate bus number to it's real value
*/
dev->link[link].subordinate = max;
busses = (busses & 0xff00ffff) |
((unsigned int)(dev->link[link].subordinate) << 16);
pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
config_busses = (config_busses & 0x00ffffff) |
(dev->link[link].subordinate << 24);
f1_write_config32(config_reg, config_busses);
{
// config config_reg, and ht_unitid_base to update hcdn_reg;
int index;
unsigned temp = 0;
index = (config_reg - 0xe0) >> 2;
for (i = 0; i < 4; i++) {
temp |= (ht_unitid_base[i] & 0xff) << (i * 8);
}
sysconf.hcdn_reg[index] = temp;
}
printk(BIOS_SPEW, "amdk8_scan_chain done\n");
return max;
}
static unsigned int amdk8_scan_chains(struct device *dev, unsigned int max)
{
unsigned nodeid;
unsigned link;
unsigned sblink = 0;
unsigned offset_unitid = 0;
nodeid = amdk8_nodeid(dev);
printk(BIOS_DEBUG, "amdk8_scan_chains\n");
if (nodeid == 0) {
sblink = (pci_read_config32(dev, 0x64) >> 8) & 3;
#if SB_HT_CHAIN_ON_BUS0 > 0
#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
offset_unitid = 1;
#endif
// do southbridge ht chain first, in case s2885 put southbridge chain (8131/8111) on link2,
// but put 8151 on link0
max =
amdk8_scan_chain(dev, nodeid, sblink, sblink, max,
offset_unitid);
#endif
}
for (link = 0; link < dev->links; link++) {
#if SB_HT_CHAIN_ON_BUS0 > 0
if ((nodeid == 0) && (sblink == link))
continue; //already done
#endif
offset_unitid = 0;
#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
if ((nodeid == 0) && (sblink == link))
#endif
offset_unitid = 1;
#endif
max = amdk8_scan_chain(dev, nodeid, link, sblink, max,
offset_unitid);
}
return max;
}
/**
* reg_useable
* @param reg register to check
* @param goal_dev device to own the resource
* @param goal_nodeid node number
* @param goal_link link number
* @return 0 if not useable, 1 if useable, or 2 if the pair is free
*/
static int reg_useable(unsigned reg,
struct device *goal_dev, unsigned goal_nodeid,
unsigned goal_link)
{
struct resource *res = NULL;
struct device *dev = NULL;
unsigned nodeid = 0, link = 0;
int result;
/* Look for the resource that matches this register. */
while (!res
&& (dev = dev_find_pci_device(PCI_VENDOR_ID_AMD, 0x1100, dev))) {
for (link = 0; !res && (link < 3); link++) {
res = probe_resource(dev, 0x100 + (reg | link));
}
nodeid++;
}
/* If no allocated resource was found, it is free - return 2 */
result = 2;
if (res) {
result = 0;
/* If the resource is allocated to the link and node already */
if ((goal_link == (link - 1)) &&
(goal_nodeid == (nodeid - 1)) && (res->flags <= 1)) {
result = 1;
}
}
return result;
}
static struct resource *amdk8_find_iopair(struct device *dev, unsigned nodeid,
unsigned link)
{
struct resource *resource;
unsigned free_reg, reg;
resource = NULL;
free_reg = 0;
for (reg = 0xc0; reg <= 0xd8; reg += 0x8) {
int result;
result = reg_useable(reg, dev, nodeid, link);
if (result == 1) {
/* I have been allocated this one */
break;
} else if (result > 1) {
/* I have a free register pair */
free_reg = reg;
}
}
if (reg > 0xd8) {
reg = free_reg;
}
if (reg > 0) {
resource = new_resource(dev, 0x100 + (reg | link));
}
return resource;
}
static struct resource *amdk8_find_mempair(struct device *dev, unsigned nodeid,
unsigned link)
{
struct resource *resource;
unsigned free_reg, reg;
resource = NULL;
free_reg = 0;
for (reg = 0x80; reg <= 0xb8; reg += 0x8) {
int result;
result = reg_useable(reg, dev, nodeid, link);
if (result == 1) {
/* I have been allocated this one */
break;
} else if (result > 1) {
/* I have a free register pair */
free_reg = reg;
}
}
if (reg > 0xb8) {
reg = free_reg;
}
if (reg > 0) {
resource = new_resource(dev, 0x100 + (reg | link));
}
return resource;
}
static void amdk8_link_read_bases(struct device *dev, unsigned nodeid,
unsigned link)
{
struct resource *resource;
/* Initialize the io space constraints on the current bus */
resource = amdk8_find_iopair(dev, nodeid, link);
if (resource) {
resource->base = 0;
resource->size = 0;
resource->align = log2c(HT_IO_HOST_ALIGN);
resource->gran = log2c(HT_IO_HOST_ALIGN);
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
}
/* Initialize the prefetchable memory constraints on the current bus */
resource = amdk8_find_mempair(dev, nodeid, link);
if (resource) {
resource->base = 0;
resource->size = 0;
resource->align = log2c(HT_MEM_HOST_ALIGN);
resource->gran = log2c(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
}
/* Initialize the memory constraints on the current bus */
resource = amdk8_find_mempair(dev, nodeid, link);
if (resource) {
resource->base = 0;
resource->size = 0;
resource->align = log2c(HT_MEM_HOST_ALIGN);
resource->gran = log2c(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffffULL;
resource->flags = IORESOURCE_MEM;
}
}
static void amdk8_read_resources(struct device *dev)
{
printk(BIOS_DEBUG, "amdk8_read_resources\n");
unsigned nodeid, link;
nodeid = amdk8_nodeid(dev);
for (link = 0; link < dev->links; link++) {
if (dev->link[link].children) {
printk(BIOS_DEBUG, "amdk8_read_resources link %d\n",
link);
amdk8_link_read_bases(dev, nodeid, link);
}
}
printk(BIOS_DEBUG, "amdk8_read_resources done\n");
}
static void amdk8_set_resource(struct device *dev, struct resource *resource,
unsigned nodeid)
{
resource_t rbase, rend;
unsigned reg, link;
char buf[50];
printk(BIOS_DEBUG, "amdk8_set_resource\n");
/* Make certain the resource has actually been set */
if (!(resource->flags & IORESOURCE_ASSIGNED)) {
return;
}
/* If I have already stored this resource don't worry about it */
if (resource->flags & IORESOURCE_STORED) {
return;
}
/* Only handle PCI memory and IO resources */
if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
return;
/* Ensure I am actually looking at a resource of function 1 */
if (resource->index < 0x100) {
return;
}
/* Get the base address */
rbase = resource->base;
/* Get the limit (rounded up) */
rend = resource_end(resource);
/* Get the register and link */
reg = resource->index & 0xfc;
link = resource->index & 3;
if (resource->flags & IORESOURCE_IO) {
u32 base, limit;
base = f1_read_config32(reg);
limit = f1_read_config32(reg + 0x4);
base &= 0xfe000fcc;
base |= rbase & 0x01fff000;
base |= 3;
limit &= 0xfe000fc8;
limit |= rend & 0x01fff000;
limit |= (link & 3) << 4;
limit |= (nodeid & 7);
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
printk(BIOS_SPEW,
"%s, enabling legacy VGA IO forwarding for %s link %x\n",
__func__, dev_path(dev), link);
base |= PCI_IO_BASE_VGA_EN;
}
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
base |= PCI_IO_BASE_NO_ISA;
}
f1_write_config32(reg + 0x4, limit);
f1_write_config32(reg, base);
} else if (resource->flags & IORESOURCE_MEM) {
u32 base, limit;
base = f1_read_config32(reg);
limit = f1_read_config32(reg + 0x4);
base &= 0x000000f0;
base |= (rbase >> 8) & 0xffffff00;
base |= 3;
limit &= 0x00000048;
limit |= (rend >> 8) & 0xffffff00;
limit |= (link & 3) << 4;
limit |= (nodeid & 7);
f1_write_config32(reg + 0x4, limit);
f1_write_config32(reg, base);
}
resource->flags |= IORESOURCE_STORED;
sprintf(buf, " <node %d link %d>", nodeid, link);
report_resource_stored(dev, resource, buf);
}
/**
*
* I tried to reuse the resource allocation code in amdk8_set_resource()
* but it is too diffcult to deal with the resource allocation magic.
*/
#ifdef CONFIG_MULTIPLE_VGA_INIT
extern struct device *vga_pri; // the primary vga device, defined in device.c
#endif
static void amdk8_create_vga_resource(struct device *dev, unsigned nodeid)
{
struct resource *resource;
unsigned link;
u32 base, limit;
unsigned reg;
/* find out which link the VGA card is connected,
* we only deal with the 'first' vga card */
for (link = 0; link < dev->links; link++) {
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
#ifdef CONFIG_MULTIPLE_VGA_INIT
printk(BIOS_DEBUG,
"VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n",
vga_pri->bus->secondary,
dev->link[link].secondary,
dev->link[link].subordinate);
/* We need to make sure the vga_pri is under the link */
if ((vga_pri->bus->secondary >=
dev->link[link].secondary)
&& (vga_pri->bus->secondary <=
dev->link[link].subordinate)
)
#endif
break;
}
}
/* no VGA card installed */
if (link == dev->links)
return;
printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n",
dev_path(dev), nodeid, link);
/* allocate a temp resrouce for legacy VGA buffer */
resource = amdk8_find_mempair(dev, nodeid, link);
if (!resource) {
printk(BIOS_DEBUG,
"VGA: Can not find free mmio reg for legacy VGA buffer\n");
return;
}
resource->base = 0xa0000;
resource->size = 0x20000;
/* write the resource to the hardware */
reg = resource->index & 0xfc;
base = f1_read_config32(reg);
limit = f1_read_config32(reg + 0x4);
base &= 0x000000f0;
base |= (resource->base >> 8) & 0xffffff00;
base |= 3;
limit &= 0x00000048;
limit |= (resource_end(resource) >> 8) & 0xffffff00;
limit |= (resource->index & 3) << 4;
limit |= (nodeid & 7);
f1_write_config32(reg + 0x4, limit);
f1_write_config32(reg, base);
/* release the temp resource */
resource->flags = 0;
}
static void amdk8_set_resources(struct device *dev)
{
unsigned nodeid, link;
int i;
/* Find the nodeid */
nodeid = amdk8_nodeid(dev);
printk(BIOS_DEBUG, "amdk8_set_resources: nodeid %d\n", nodeid);
amdk8_create_vga_resource(dev, nodeid);
/* Set each resource we have found */
for (i = 0; i < dev->resources; i++) {
amdk8_set_resource(dev, &dev->resource[i], nodeid);
}
for (link = 0; link < dev->links; link++) {
struct bus *bus;
bus = &dev->link[link];
if (bus->children) {
phase4_set_resources(bus);
}
}
}
static void amdk8_enable_resources(struct device *dev)
{
printk(BIOS_DEBUG, "amdk8_enable_resources\n");
pci_dev_enable_resources(dev);
enable_childrens_resources(dev);
}
static void mcf0_control_init(struct device *dev)
{
printk(BIOS_DEBUG, "NB: Function 0 Misc Control.. Nothing to do ...");
@ -585,21 +53,15 @@ static void mcf0_control_init(struct device *dev)
printk(BIOS_DEBUG, "done.\n");
}
#ifdef CONFIG_PCI_64BIT_PREF_MEM
#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH)
#endif
struct device_operations k8_ops = {
.id = {.type = DEVICE_ID_PCI,
{.pci = {.vendor = PCI_VENDOR_ID_AMD,
.device = 0x1100}}},
.constructor = default_device_constructor,
.reset_bus = pci_bus_reset,
.phase3_scan = amdk8_scan_chains,
.phase4_read_resources = amdk8_read_resources,
.phase4_set_resources = amdk8_set_resources,
.phase5_enable_resources = amdk8_enable_resources,
.phase3_scan = NULL,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = mcf0_control_init,
.ops_pci = &pci_dev_ops_pci,
.ops_pci_bus = &pci_cf8_conf1,
};