From bd93211bb8df98bf4ac89c74464058e67f36a865 Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Wed, 2 Sep 2015 18:10:14 -0700 Subject: [PATCH] rk3288: Allow board-specific APLL (CPU clock) settings This changes the API to rkclk_configure_cpu() such that we can pass in the desired APLL frequency in each veyron board's bootblock.c. Devices with a constrainted form facter (rialto and possibly mickey) will use this to run firmware at a slower speed to mitigate risk of thermal issues (due to the RK808, not the RK3288). BUG=chrome-os-partner:42054 BRANCH=firmware-veyron TEST=amstan says rialto is noticably cooler (and slower) Signed-off-by: David Hendricks Reviewed-on: https://chromium-review.googlesource.com/297190 Reviewed-by: Julius Werner Change-Id: I960cb6ff512c058e72032aa2cbadedde97510631 Reviewed-on: https://chromium-review.googlesource.com/299714 --- src/mainboard/google/veyron_brain/bootblock.c | 2 +- src/mainboard/google/veyron_danger/bootblock.c | 2 +- src/mainboard/google/veyron_gus/bootblock.c | 2 +- src/mainboard/google/veyron_jaq/bootblock.c | 2 +- src/mainboard/google/veyron_jerry/bootblock.c | 2 +- src/mainboard/google/veyron_mickey/bootblock.c | 2 +- src/mainboard/google/veyron_mighty/bootblock.c | 2 +- src/mainboard/google/veyron_minnie/bootblock.c | 2 +- src/mainboard/google/veyron_nicky/bootblock.c | 2 +- src/mainboard/google/veyron_pinky/bootblock.c | 2 +- src/mainboard/google/veyron_romy/bootblock.c | 2 +- src/mainboard/google/veyron_speedy/bootblock.c | 2 +- src/mainboard/google/veyron_thea/bootblock.c | 2 +- src/soc/rockchip/rk3288/clock.c | 13 ++++++++++--- src/soc/rockchip/rk3288/include/soc/clock.h | 8 ++++++-- 15 files changed, 29 insertions(+), 18 deletions(-) diff --git a/src/mainboard/google/veyron_brain/bootblock.c b/src/mainboard/google/veyron_brain/bootblock.c index 1169455871..57c76f8efc 100644 --- a/src/mainboard/google/veyron_brain/bootblock.c +++ b/src/mainboard/google/veyron_brain/bootblock.c @@ -61,7 +61,7 @@ void bootblock_mainboard_init(void) udelay(175);/* Must wait for voltage to stabilize,2mV/us */ rk808_configure_buck(1, 1400); udelay(100);/* Must wait for voltage to stabilize,2mV/us */ - rkclk_configure_cpu(); + rkclk_configure_cpu(APLL_1800_MHZ); /* i2c1 for tpm */ writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); diff --git a/src/mainboard/google/veyron_danger/bootblock.c b/src/mainboard/google/veyron_danger/bootblock.c index 610c23e4de..7ff5b78a07 100644 --- a/src/mainboard/google/veyron_danger/bootblock.c +++ b/src/mainboard/google/veyron_danger/bootblock.c @@ -58,7 +58,7 @@ void bootblock_mainboard_init(void) udelay(175);/* Must wait for voltage to stabilize,2mV/us */ rk808_configure_buck(1, 1400); udelay(100);/* Must wait for voltage to stabilize,2mV/us */ - rkclk_configure_cpu(); + rkclk_configure_cpu(APLL_1800_MHZ); if (rkclk_was_watchdog_reset()) { printk(BIOS_INFO, "Last reset was watchdog... rebooting via GPIO!\n"); diff --git a/src/mainboard/google/veyron_gus/bootblock.c b/src/mainboard/google/veyron_gus/bootblock.c index 1bc8840ade..ebef491a41 100644 --- a/src/mainboard/google/veyron_gus/bootblock.c +++ b/src/mainboard/google/veyron_gus/bootblock.c @@ -59,7 +59,7 @@ void bootblock_mainboard_init(void) udelay(175);/* Must wait for voltage to stabilize,2mV/us */ rk808_configure_buck(1, 1400); udelay(100);/* Must wait for voltage to stabilize,2mV/us */ - rkclk_configure_cpu(); + rkclk_configure_cpu(APLL_1800_MHZ); /* i2c1 for tpm */ writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); diff --git a/src/mainboard/google/veyron_jaq/bootblock.c b/src/mainboard/google/veyron_jaq/bootblock.c index 1bc8840ade..ebef491a41 100644 --- a/src/mainboard/google/veyron_jaq/bootblock.c +++ b/src/mainboard/google/veyron_jaq/bootblock.c @@ -59,7 +59,7 @@ void bootblock_mainboard_init(void) udelay(175);/* Must wait for voltage to stabilize,2mV/us */ rk808_configure_buck(1, 1400); udelay(100);/* Must wait for voltage to stabilize,2mV/us */ - rkclk_configure_cpu(); + rkclk_configure_cpu(APLL_1800_MHZ); /* i2c1 for tpm */ writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); diff --git a/src/mainboard/google/veyron_jerry/bootblock.c b/src/mainboard/google/veyron_jerry/bootblock.c index 1bc8840ade..ebef491a41 100644 --- a/src/mainboard/google/veyron_jerry/bootblock.c +++ b/src/mainboard/google/veyron_jerry/bootblock.c @@ -59,7 +59,7 @@ void bootblock_mainboard_init(void) udelay(175);/* Must wait for voltage to stabilize,2mV/us */ rk808_configure_buck(1, 1400); udelay(100);/* Must wait for voltage to stabilize,2mV/us */ - rkclk_configure_cpu(); + rkclk_configure_cpu(APLL_1800_MHZ); /* i2c1 for tpm */ writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); diff --git a/src/mainboard/google/veyron_mickey/bootblock.c b/src/mainboard/google/veyron_mickey/bootblock.c index 1169455871..57c76f8efc 100644 --- a/src/mainboard/google/veyron_mickey/bootblock.c +++ b/src/mainboard/google/veyron_mickey/bootblock.c @@ -61,7 +61,7 @@ void bootblock_mainboard_init(void) udelay(175);/* Must wait for voltage to stabilize,2mV/us */ rk808_configure_buck(1, 1400); udelay(100);/* Must wait for voltage to stabilize,2mV/us */ - rkclk_configure_cpu(); + rkclk_configure_cpu(APLL_1800_MHZ); /* i2c1 for tpm */ writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); diff --git a/src/mainboard/google/veyron_mighty/bootblock.c b/src/mainboard/google/veyron_mighty/bootblock.c index 1bc8840ade..ebef491a41 100644 --- a/src/mainboard/google/veyron_mighty/bootblock.c +++ b/src/mainboard/google/veyron_mighty/bootblock.c @@ -59,7 +59,7 @@ void bootblock_mainboard_init(void) udelay(175);/* Must wait for voltage to stabilize,2mV/us */ rk808_configure_buck(1, 1400); udelay(100);/* Must wait for voltage to stabilize,2mV/us */ - rkclk_configure_cpu(); + rkclk_configure_cpu(APLL_1800_MHZ); /* i2c1 for tpm */ writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); diff --git a/src/mainboard/google/veyron_minnie/bootblock.c b/src/mainboard/google/veyron_minnie/bootblock.c index 1bc8840ade..ebef491a41 100644 --- a/src/mainboard/google/veyron_minnie/bootblock.c +++ b/src/mainboard/google/veyron_minnie/bootblock.c @@ -59,7 +59,7 @@ void bootblock_mainboard_init(void) udelay(175);/* Must wait for voltage to stabilize,2mV/us */ rk808_configure_buck(1, 1400); udelay(100);/* Must wait for voltage to stabilize,2mV/us */ - rkclk_configure_cpu(); + rkclk_configure_cpu(APLL_1800_MHZ); /* i2c1 for tpm */ writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); diff --git a/src/mainboard/google/veyron_nicky/bootblock.c b/src/mainboard/google/veyron_nicky/bootblock.c index 1bc8840ade..ebef491a41 100644 --- a/src/mainboard/google/veyron_nicky/bootblock.c +++ b/src/mainboard/google/veyron_nicky/bootblock.c @@ -59,7 +59,7 @@ void bootblock_mainboard_init(void) udelay(175);/* Must wait for voltage to stabilize,2mV/us */ rk808_configure_buck(1, 1400); udelay(100);/* Must wait for voltage to stabilize,2mV/us */ - rkclk_configure_cpu(); + rkclk_configure_cpu(APLL_1800_MHZ); /* i2c1 for tpm */ writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c index 1bc8840ade..ebef491a41 100644 --- a/src/mainboard/google/veyron_pinky/bootblock.c +++ b/src/mainboard/google/veyron_pinky/bootblock.c @@ -59,7 +59,7 @@ void bootblock_mainboard_init(void) udelay(175);/* Must wait for voltage to stabilize,2mV/us */ rk808_configure_buck(1, 1400); udelay(100);/* Must wait for voltage to stabilize,2mV/us */ - rkclk_configure_cpu(); + rkclk_configure_cpu(APLL_1800_MHZ); /* i2c1 for tpm */ writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); diff --git a/src/mainboard/google/veyron_romy/bootblock.c b/src/mainboard/google/veyron_romy/bootblock.c index 1169455871..57c76f8efc 100644 --- a/src/mainboard/google/veyron_romy/bootblock.c +++ b/src/mainboard/google/veyron_romy/bootblock.c @@ -61,7 +61,7 @@ void bootblock_mainboard_init(void) udelay(175);/* Must wait for voltage to stabilize,2mV/us */ rk808_configure_buck(1, 1400); udelay(100);/* Must wait for voltage to stabilize,2mV/us */ - rkclk_configure_cpu(); + rkclk_configure_cpu(APLL_1800_MHZ); /* i2c1 for tpm */ writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); diff --git a/src/mainboard/google/veyron_speedy/bootblock.c b/src/mainboard/google/veyron_speedy/bootblock.c index 1bc8840ade..ebef491a41 100644 --- a/src/mainboard/google/veyron_speedy/bootblock.c +++ b/src/mainboard/google/veyron_speedy/bootblock.c @@ -59,7 +59,7 @@ void bootblock_mainboard_init(void) udelay(175);/* Must wait for voltage to stabilize,2mV/us */ rk808_configure_buck(1, 1400); udelay(100);/* Must wait for voltage to stabilize,2mV/us */ - rkclk_configure_cpu(); + rkclk_configure_cpu(APLL_1800_MHZ); /* i2c1 for tpm */ writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); diff --git a/src/mainboard/google/veyron_thea/bootblock.c b/src/mainboard/google/veyron_thea/bootblock.c index 1bc8840ade..ebef491a41 100644 --- a/src/mainboard/google/veyron_thea/bootblock.c +++ b/src/mainboard/google/veyron_thea/bootblock.c @@ -59,7 +59,7 @@ void bootblock_mainboard_init(void) udelay(175);/* Must wait for voltage to stabilize,2mV/us */ rk808_configure_buck(1, 1400); udelay(100);/* Must wait for voltage to stabilize,2mV/us */ - rkclk_configure_cpu(); + rkclk_configure_cpu(APLL_1800_MHZ); /* i2c1 for tpm */ writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index 4b07beb88b..642dc5b21b 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -72,10 +72,17 @@ static struct rk3288_cru_reg * const cru_ptr = (void *)CRU_BASE; "divisors on line " STRINGIFY(__LINE__)); /* Keep divisors as low as possible to reduce jitter and power usage. */ -static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1); static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); +/* See linux/drivers/clk/rockchip/clk-rk3288.c for more APLL combinations */ +static const struct pll_div apll_1800_cfg = PLL_DIVISORS(1800*MHz, 1, 1); +static const struct pll_div apll_1392_cfg = PLL_DIVISORS(1392*MHz, 1, 1); +static const struct pll_div *apll_cfgs[] = { + [APLL_1800_MHZ] = &apll_1800_cfg, + [APLL_1392_MHZ] = &apll_1392_cfg, +}; + /*******************PLL CON0 BITS***************************/ #define PLL_OD_MSK (0x0F) @@ -329,13 +336,13 @@ void rkclk_init(void) } -void rkclk_configure_cpu(void) +void rkclk_configure_cpu(enum apll_frequencies apll_freq) { /* pll enter slow-mode */ writel(RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_SLOW), &cru_ptr->cru_mode_con); - rkclk_set_pll(&cru_ptr->cru_apll_con[0], &apll_init_cfg); + rkclk_set_pll(&cru_ptr->cru_apll_con[0], apll_cfgs[apll_freq]); /* waiting for pll lock */ while (1) { diff --git a/src/soc/rockchip/rk3288/include/soc/clock.h b/src/soc/rockchip/rk3288/include/soc/clock.h index 9a376b72de..dc9cf5ef36 100644 --- a/src/soc/rockchip/rk3288/include/soc/clock.h +++ b/src/soc/rockchip/rk3288/include/soc/clock.h @@ -24,11 +24,15 @@ #define OSC_HZ (24*MHz) -#define APLL_HZ (1800*MHz) #define GPLL_HZ (594*MHz) #define CPLL_HZ (384*MHz) #define NPLL_HZ (384*MHz) +enum apll_frequencies { + APLL_1800_MHZ, + APLL_1392_MHZ, +}; + /* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed. */ #define PD_BUS_ACLK_HZ (297000*KHz) #define PD_BUS_HCLK_HZ (148500*KHz) @@ -44,7 +48,7 @@ void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy); void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n); void rkclk_configure_ddr(unsigned int hz); void rkclk_configure_i2s(unsigned int hz); -void rkclk_configure_cpu(void); +void rkclk_configure_cpu(enum apll_frequencies apll_freq); void rkclk_configure_crypto(unsigned int hz); void rkclk_configure_tsadc(unsigned int hz); void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz);