erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Replace hlt() loops with halt()

Browse source 
Change-Id: I8486e70615f4c404a342cb86963b5357a934c41d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7606
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Patrick Georgi 2014-11-28 22:35:36 +01:00
commit bd79c5eaf1
25 changed files with 60 additions and 77 deletions
Download patch file Download diff file Expand all files Collapse all files

5
src/cpu/intel/haswell/romstage.c
View file

@ -25,6 +25,7 @@
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <halt.h>
#include <lib.h>
#include <timestamp.h>
#include <arch/io.h>
@ -49,9 +50,7 @@
static inline void reset_system(void)
{
hard_reset();
while (1) {
hlt();
}
halt();
}
/* The cache-as-ram assembly file calls romstage_main() after setting up

6
src/cpu/x86/lapic/lapic_cpu_init.c
View file

@ -23,10 +23,10 @@
#include <cpu/x86/cr.h>
#include <cpu/x86/lapic.h>
#include <delay.h>
#include <halt.h>
#include <lib.h>
#include <string.h>
#include <console/console.h>
#include <arch/hlt.h>
#include <device/device.h>
#include <device/path.h>
#include <smp/atomic.h>
@ -396,9 +396,7 @@ void stop_this_cpu(void)
#endif
}
while(1) {
hlt();
}
halt();
}
#endif