From bd634f386089fd281398fe7c22a00ff14ca5968c Mon Sep 17 00:00:00 2001 From: Ivy Jian Date: Tue, 3 Feb 2026 14:59:26 +0800 Subject: [PATCH] mb/google/ocelot/matsu: Remove RTD3 config for SSD The Matsu hardware design does not have a power load switch for the SSD. Without it, the platform cannot cut off the main power rail to the device to enter D3cold. Therefore, remove the RTD3 chip driver and its associated GPIO configurations (enable/reset) in the overridetree to align with the hardware capability. The system will support D3hot instead of D3cold. BUG=443612246 TEST=Build and boot to OS on Matsu, verify SSD still functions correctly and power state transitions align with HW design. Change-Id: I84db81c17afffafbdb6c7abcc752009c824bc2ed Signed-off-by: Ivy Jian Reviewed-on: https://review.coreboot.org/c/coreboot/+/91086 Reviewed-by: Pranava Y N Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/mainboard/google/ocelot/variants/matsu/overridetree.cb | 7 ------- 1 file changed, 7 deletions(-) diff --git a/src/mainboard/google/ocelot/variants/matsu/overridetree.cb b/src/mainboard/google/ocelot/variants/matsu/overridetree.cb index 59d6226735..8da38fe1d8 100644 --- a/src/mainboard/google/ocelot/variants/matsu/overridetree.cb +++ b/src/mainboard/google/ocelot/variants/matsu/overridetree.cb @@ -337,13 +337,6 @@ chip soc/intel/pantherlake .clk_req = 3, .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, }" - chip soc/intel/common/block/pcie/rtd3 - register "is_storage" = "true" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H18)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A08)" - register "srcclk_pin" = "3" - device generic 0 on end - end end # Gen4 M.2 SSD device ref cnvi_wifi on