From bcbe17dea3c004f85abd0e56b51f0df0aab6bd67 Mon Sep 17 00:00:00 2001 From: Wentao Qin Date: Tue, 11 Feb 2025 14:44:54 +0800 Subject: [PATCH] mb/google/skywalker: Configure TPM Initialize I2C bus 3 for TPM control and enable vboot secdata. BUG=b:395723580 BRANCH=none TEST=check boot log Change-Id: I34da1a494e71bdaac0223d1db918fffe12f68df4 Signed-off-by: Wentao Qin Reviewed-on: https://review.coreboot.org/c/coreboot/+/87772 Reviewed-by: Yu-Ping Wu Reviewed-by: Yidi Lin Tested-by: build bot (Jenkins) --- src/mainboard/google/skywalker/Kconfig | 13 +++++++++++-- src/mainboard/google/skywalker/bootblock.c | 4 ++++ src/mainboard/google/skywalker/chromeos.c | 8 ++++++++ src/mainboard/google/skywalker/gpio.h | 1 + 4 files changed, 24 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/skywalker/Kconfig b/src/mainboard/google/skywalker/Kconfig index 4287636c82..2bdb0df18a 100644 --- a/src/mainboard/google/skywalker/Kconfig +++ b/src/mainboard/google/skywalker/Kconfig @@ -11,8 +11,6 @@ if BOARD_GOOGLE_SKYWALKER_COMMON config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_VBNV_FLASH - select VBOOT_NO_BOARD_SUPPORT - select VBOOT_MOCK_SECDATA config BOARD_SPECIFIC_OPTIONS def_bool y @@ -26,6 +24,9 @@ config BOARD_SPECIFIC_OPTIONS select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_SPI + select I2C_TPM if VBOOT + select MAINBOARD_HAS_TPM2 if VBOOT + select TPM_GOOGLE_TI50 if VBOOT select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI select RTC @@ -48,4 +49,12 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 0x0 +config DRIVER_TPM_I2C_BUS + hex + default 0x3 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x50 + endif diff --git a/src/mainboard/google/skywalker/bootblock.c b/src/mainboard/google/skywalker/bootblock.c index b090924b77..330bd6a541 100644 --- a/src/mainboard/google/skywalker/bootblock.c +++ b/src/mainboard/google/skywalker/bootblock.c @@ -2,6 +2,8 @@ #include #include +#include +#include #include #include "gpio.h" @@ -13,8 +15,10 @@ static void usb3_hub_reset(void) void bootblock_mainboard_init(void) { + mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST_PLUS); mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0); mtk_snfc_init(); usb3_hub_reset(); setup_chromeos_gpios(); + gpio_eint_configure(GPIO_GSC_AP_INT_ODL, IRQ_TYPE_EDGE_RISING); } diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c index 6c7aca8917..eb310f3576 100644 --- a/src/mainboard/google/skywalker/chromeos.c +++ b/src/mainboard/google/skywalker/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ #include +#include #include #include @@ -9,6 +10,7 @@ void setup_chromeos_gpios(void) { gpio_input(GPIO_EC_AP_INT_ODL); + gpio_input(GPIO_GSC_AP_INT_ODL); gpio_output(GPIO_AP_EC_WARM_RST_REQ, 0); gpio_output(GPIO_XHCI_INIT_DONE, 0); } @@ -18,6 +20,12 @@ void fill_lb_gpios(struct lb_gpios *gpios) struct lb_gpio chromeos_gpios[] = { {GPIO_XHCI_INIT_DONE.id, ACTIVE_HIGH, -1, "XHCI init done"}, {GPIO_EC_AP_INT_ODL.id, ACTIVE_LOW, -1, "EC interrupt"}, + {GPIO_GSC_AP_INT_ODL.id, ACTIVE_HIGH, -1, "TPM interrupt"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } + +int cr50_plat_irq_status(void) +{ + return gpio_eint_poll(GPIO_GSC_AP_INT_ODL); +} diff --git a/src/mainboard/google/skywalker/gpio.h b/src/mainboard/google/skywalker/gpio.h index da1622edc0..1fc4674de5 100644 --- a/src/mainboard/google/skywalker/gpio.h +++ b/src/mainboard/google/skywalker/gpio.h @@ -9,6 +9,7 @@ #define GPIO_USB3_HUB_RST_L GPIO(GPIO07) #define GPIO_EC_AP_INT_ODL GPIO(GBE_MDIO) #define GPIO_AP_EC_WARM_RST_REQ GPIO(GBE_AUX_PPS0) +#define GPIO_GSC_AP_INT_ODL GPIO(GBE_AUX_PPS1) void setup_chromeos_gpios(void);