From bc2ba9c15cfd22aeaca4f80b1d13a8b5e0178ead Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 20 Oct 2013 22:15:33 -0700 Subject: [PATCH] tegra124: When setting up the main CPU, set its CPSR appropriately. The CPSR isn't set up in the bootblock like it normally would be since the bootblock executes on the AVP and not the main CPUs like the remainder of the firmware. BUG=None TEST=Built and booted into depthcharge on nyan. BRANCH=None Change-Id: I5b2fa460b6be6b212418de381e92de9b2fad70cb Signed-off-by: Gabe Black Reviewed-on: https://chromium-review.googlesource.com/173775 Reviewed-by: Hung-Te Lin Commit-Queue: Gabe Black Tested-by: Gabe Black --- src/soc/nvidia/tegra124/cpug.S | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/soc/nvidia/tegra124/cpug.S b/src/soc/nvidia/tegra124/cpug.S index eceb66baf7..7f761e8de4 100644 --- a/src/soc/nvidia/tegra124/cpug.S +++ b/src/soc/nvidia/tegra124/cpug.S @@ -41,6 +41,15 @@ cpug_entry_point: .global cpug_setup .type cpug_setup, function cpug_setup: + + /* + * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data + * aborts may happen early and crash before the abort handlers are + * installed, but at least the problem will show up near the code that + * causes it. + */ + msr cpsr_cxf, #0xdf + ldr sp, cpug_stack_pointer eor lr, lr ldr r0, cpug_entry_point