diff --git a/src/soc/intel/broadwell/acpi/cpu.asl b/src/soc/intel/broadwell/acpi/cpu.asl index 648ebcd120..f0da2dedd6 100644 --- a/src/soc/intel/broadwell/acpi/cpu.asl +++ b/src/soc/intel/broadwell/acpi/cpu.asl @@ -88,13 +88,35 @@ Method (TNOT) Method (PPKG) { If (LGreaterEqual (\PCNT, 8)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3, - \_PR.CPU4, \_PR.CPU5, \_PR.CPU6, \_PR.CPU7}) + Return (Package() + { + \_PR.CPU0, + \_PR.CPU1, + \_PR.CPU2, + \_PR.CPU3, + \_PR.CPU4, + \_PR.CPU5, + \_PR.CPU6, + \_PR.CPU7 + }) } ElseIf (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3}) + Return (Package () + { + \_PR.CPU0, + \_PR.CPU1, + \_PR.CPU2, + \_PR.CPU3 + }) } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package () + { + \_PR.CPU0, + \_PR.CPU1 + }) } Else { - Return (Package() {\_PR.CPU0}) + Return (Package () + { + \_PR.CPU0 + }) } } diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/acpi/globalnvs.asl index 7849de6504..413c811fe6 100644 --- a/src/soc/intel/broadwell/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/acpi/globalnvs.asl @@ -20,10 +20,10 @@ /* Global Variables */ -Name(\PICM, 0) // IOAPIC/8259 -Name(\DSEN, 1) // Display Output Switching Enable +Name (\PICM, 0) // IOAPIC/8259 -/* Global ACPI memory region. This region is used for passing information +/* + * Global ACPI memory region. This region is used for passing information * between coreboot (aka "the system bios"), ACPI, and the SMI handler. * Since we don't know where this will end up in memory at ACPI compile time, * we have to fix it up in coreboot's ACPI creation phase. diff --git a/src/soc/intel/broadwell/acpi/irqlinks.asl b/src/soc/intel/broadwell/acpi/irqlinks.asl index 02a3bfab4f..fee400e6d7 100644 --- a/src/soc/intel/broadwell/acpi/irqlinks.asl +++ b/src/soc/intel/broadwell/acpi/irqlinks.asl @@ -32,7 +32,7 @@ Device (LNKA) // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) + IRQ (Level, ActiveLow, Shared) { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } }) @@ -41,15 +41,15 @@ Device (LNKA) { Name (RTLA, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) {} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField(RTLA, 1, IRQ0) + CreateWordField (RTLA, 1, IRQ0) // Clear the WordField Store (Zero, IRQ0) // Set the bit from PRTA - ShiftLeft(1, And(PRTA, 0x0f), IRQ0) + ShiftLeft (1, And (PRTA, 0x0f), IRQ0) Return (RTLA) } @@ -57,19 +57,19 @@ Device (LNKA) // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { - CreateWordField(Arg0, 1, IRQ0) + CreateWordField (Arg0, 1, IRQ0) // Which bit is set? - FindSetRightBit(IRQ0, Local0) + FindSetRightBit (IRQ0, Local0) Decrement(Local0) - Store(Local0, PRTA) + Store (Local0, PRTA) } // Status Method (_STA, 0, Serialized) { - If(And(PRTA, 0x80)) { + If(And (PRTA, 0x80)) { Return (0x9) } Else { Return (0xb) @@ -91,7 +91,7 @@ Device (LNKB) // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) + IRQ (Level, ActiveLow, Shared) { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } }) @@ -100,15 +100,15 @@ Device (LNKB) { Name (RTLB, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) {} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField(RTLB, 1, IRQ0) + CreateWordField (RTLB, 1, IRQ0) // Clear the WordField Store (Zero, IRQ0) // Set the bit from PRTB - ShiftLeft(1, And(PRTB, 0x0f), IRQ0) + ShiftLeft (1, And (PRTB, 0x0f), IRQ0) Return (RTLB) } @@ -116,19 +116,19 @@ Device (LNKB) // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { - CreateWordField(Arg0, 1, IRQ0) + CreateWordField (Arg0, 1, IRQ0) // Which bit is set? - FindSetRightBit(IRQ0, Local0) + FindSetRightBit (IRQ0, Local0) Decrement(Local0) - Store(Local0, PRTB) + Store (Local0, PRTB) } // Status Method (_STA, 0, Serialized) { - If(And(PRTB, 0x80)) { + If(And (PRTB, 0x80)) { Return (0x9) } Else { Return (0xb) @@ -150,7 +150,7 @@ Device (LNKC) // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) + IRQ (Level, ActiveLow, Shared) { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } }) @@ -159,15 +159,15 @@ Device (LNKC) { Name (RTLC, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) {} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField(RTLC, 1, IRQ0) + CreateWordField (RTLC, 1, IRQ0) // Clear the WordField Store (Zero, IRQ0) // Set the bit from PRTC - ShiftLeft(1, And(PRTC, 0x0f), IRQ0) + ShiftLeft (1, And (PRTC, 0x0f), IRQ0) Return (RTLC) } @@ -175,19 +175,19 @@ Device (LNKC) // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { - CreateWordField(Arg0, 1, IRQ0) + CreateWordField (Arg0, 1, IRQ0) // Which bit is set? - FindSetRightBit(IRQ0, Local0) + FindSetRightBit (IRQ0, Local0) Decrement(Local0) - Store(Local0, PRTC) + Store (Local0, PRTC) } // Status Method (_STA, 0, Serialized) { - If(And(PRTC, 0x80)) { + If(And (PRTC, 0x80)) { Return (0x9) } Else { Return (0xb) @@ -209,7 +209,7 @@ Device (LNKD) // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) + IRQ (Level, ActiveLow, Shared) { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } }) @@ -218,15 +218,15 @@ Device (LNKD) { Name (RTLD, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) {} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField(RTLD, 1, IRQ0) + CreateWordField (RTLD, 1, IRQ0) // Clear the WordField Store (Zero, IRQ0) // Set the bit from PRTD - ShiftLeft(1, And(PRTD, 0x0f), IRQ0) + ShiftLeft (1, And (PRTD, 0x0f), IRQ0) Return (RTLD) } @@ -234,19 +234,19 @@ Device (LNKD) // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { - CreateWordField(Arg0, 1, IRQ0) + CreateWordField (Arg0, 1, IRQ0) // Which bit is set? - FindSetRightBit(IRQ0, Local0) + FindSetRightBit (IRQ0, Local0) Decrement(Local0) - Store(Local0, PRTD) + Store (Local0, PRTD) } // Status Method (_STA, 0, Serialized) { - If(And(PRTD, 0x80)) { + If(And (PRTD, 0x80)) { Return (0x9) } Else { Return (0xb) @@ -268,7 +268,7 @@ Device (LNKE) // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) + IRQ (Level, ActiveLow, Shared) { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } }) @@ -277,15 +277,15 @@ Device (LNKE) { Name (RTLE, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) {} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField(RTLE, 1, IRQ0) + CreateWordField (RTLE, 1, IRQ0) // Clear the WordField Store (Zero, IRQ0) // Set the bit from PRTE - ShiftLeft(1, And(PRTE, 0x0f), IRQ0) + ShiftLeft (1, And (PRTE, 0x0f), IRQ0) Return (RTLE) } @@ -293,19 +293,19 @@ Device (LNKE) // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { - CreateWordField(Arg0, 1, IRQ0) + CreateWordField (Arg0, 1, IRQ0) // Which bit is set? - FindSetRightBit(IRQ0, Local0) + FindSetRightBit (IRQ0, Local0) Decrement(Local0) - Store(Local0, PRTE) + Store (Local0, PRTE) } // Status Method (_STA, 0, Serialized) { - If(And(PRTE, 0x80)) { + If(And (PRTE, 0x80)) { Return (0x9) } Else { Return (0xb) @@ -327,7 +327,7 @@ Device (LNKF) // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) + IRQ (Level, ActiveLow, Shared) { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } }) @@ -336,15 +336,15 @@ Device (LNKF) { Name (RTLF, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) {} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField(RTLF, 1, IRQ0) + CreateWordField (RTLF, 1, IRQ0) // Clear the WordField Store (Zero, IRQ0) // Set the bit from PRTF - ShiftLeft(1, And(PRTF, 0x0f), IRQ0) + ShiftLeft (1, And (PRTF, 0x0f), IRQ0) Return (RTLF) } @@ -352,19 +352,19 @@ Device (LNKF) // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { - CreateWordField(Arg0, 1, IRQ0) + CreateWordField (Arg0, 1, IRQ0) // Which bit is set? - FindSetRightBit(IRQ0, Local0) + FindSetRightBit (IRQ0, Local0) Decrement(Local0) - Store(Local0, PRTF) + Store (Local0, PRTF) } // Status Method (_STA, 0, Serialized) { - If(And(PRTF, 0x80)) { + If(And (PRTF, 0x80)) { Return (0x9) } Else { Return (0xb) @@ -386,7 +386,7 @@ Device (LNKG) // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) + IRQ (Level, ActiveLow, Shared) { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } }) @@ -395,15 +395,15 @@ Device (LNKG) { Name (RTLG, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) {} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField(RTLG, 1, IRQ0) + CreateWordField (RTLG, 1, IRQ0) // Clear the WordField Store (Zero, IRQ0) // Set the bit from PRTG - ShiftLeft(1, And(PRTG, 0x0f), IRQ0) + ShiftLeft (1, And (PRTG, 0x0f), IRQ0) Return (RTLG) } @@ -411,19 +411,19 @@ Device (LNKG) // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { - CreateWordField(Arg0, 1, IRQ0) + CreateWordField (Arg0, 1, IRQ0) // Which bit is set? - FindSetRightBit(IRQ0, Local0) + FindSetRightBit (IRQ0, Local0) Decrement(Local0) - Store(Local0, PRTG) + Store (Local0, PRTG) } // Status Method (_STA, 0, Serialized) { - If(And(PRTG, 0x80)) { + If(And (PRTG, 0x80)) { Return (0x9) } Else { Return (0xb) @@ -445,7 +445,7 @@ Device (LNKH) // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) + IRQ (Level, ActiveLow, Shared) { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } }) @@ -454,15 +454,15 @@ Device (LNKH) { Name (RTLH, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) {} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField(RTLH, 1, IRQ0) + CreateWordField (RTLH, 1, IRQ0) // Clear the WordField Store (Zero, IRQ0) // Set the bit from PRTH - ShiftLeft(1, And(PRTH, 0x0f), IRQ0) + ShiftLeft (1, And (PRTH, 0x0f), IRQ0) Return (RTLH) } @@ -470,19 +470,19 @@ Device (LNKH) // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { - CreateWordField(Arg0, 1, IRQ0) + CreateWordField (Arg0, 1, IRQ0) // Which bit is set? - FindSetRightBit(IRQ0, Local0) + FindSetRightBit (IRQ0, Local0) Decrement(Local0) - Store(Local0, PRTH) + Store (Local0, PRTH) } // Status Method (_STA, 0, Serialized) { - If(And(PRTH, 0x80)) { + If(And (PRTH, 0x80)) { Return (0x9) } Else { Return (0xb) diff --git a/src/soc/intel/broadwell/acpi/lpc.asl b/src/soc/intel/broadwell/acpi/lpc.asl index 1357e460ab..2f27d9b252 100644 --- a/src/soc/intel/broadwell/acpi/lpc.asl +++ b/src/soc/intel/broadwell/acpi/lpc.asl @@ -22,13 +22,11 @@ Device (LPCB) { - Name(_ADR, 0x001f0000) + Name (_ADR, 0x001f0000) OperationRegion(LPC0, PCI_Config, 0x00, 0x100) Field (LPC0, AnyAcc, NoLock, Preserve) { - Offset (0x3), - DIDH, 8, // Device ID High Byte Offset (0x40), PMBS, 16, // PMBASE Offset (0x48), @@ -47,21 +45,12 @@ Device (LPCB) Offset (0x80), // IO Decode Ranges IOD0, 8, IOD1, 8, - - Offset (0xf0), // RCBA - RCEN, 1, - , 13, - RCBA, 18, } - #include "irqlinks.asl" - - #include "acpi/ec.asl" - - Device (DMAC) // DMA Controller + Device (DMAC) // DMA Controller { - Name(_HID, EISAID("PNP0200")) - Name(_CRS, ResourceTemplate() + Name (_HID, EISAID("PNP0200")) + Name (_CRS, ResourceTemplate() { IO (Decode16, 0x00, 0x00, 0x01, 0x20) IO (Decode16, 0x81, 0x81, 0x01, 0x11) @@ -71,7 +60,7 @@ Device (LPCB) }) } - Device (FWH) // Firmware Hub + Device (FWH) // Firmware Hub { Name (_HID, EISAID("INT0800")) Name (_CRS, ResourceTemplate() @@ -85,7 +74,7 @@ Device (LPCB) Name (_HID, EISAID("PNP0103")) Name (_CID, 0x010CD041) - Name(BUF0, ResourceTemplate() + Name (BUF0, ResourceTemplate() { Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0) }) @@ -108,7 +97,9 @@ Device (LPCB) Method (_CRS, 0, Serialized) // Current resources { If (HPTE) { - CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) + CreateDWordField (BUF0, + \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) + If (Lequal(HPAS, 1)) { Store(0xfed01000, HPT0) } @@ -128,8 +119,8 @@ Device (LPCB) Device(PIC) // 8259 Interrupt Controller { - Name(_HID,EISAID("PNP0000")) - Name(_CRS, ResourceTemplate() + Name (_HID,EISAID("PNP0000")) + Name (_CRS, ResourceTemplate() { IO (Decode16, 0x20, 0x20, 0x01, 0x02) IO (Decode16, 0x24, 0x24, 0x01, 0x02) @@ -194,46 +185,45 @@ Device (LPCB) Name (_CRS, ResourceTemplate() { IO (Decode16, 0x70, 0x70, 1, 8) -// Disable as Windows doesn't like it, and systems don't seem to use it. -// IRQNoFlags() { 8 } + //IRQNoFlags() { 8 } }) } Device (TIMR) // Intel 8254 timer { - Name(_HID, EISAID("PNP0100")) - Name(_CRS, ResourceTemplate() - { + Name (_HID, EISAID("PNP0100")) + Name (_CRS, ResourceTemplate() { IO (Decode16, 0x40, 0x40, 0x01, 0x04) IO (Decode16, 0x50, 0x50, 0x10, 0x04) IRQNoFlags() {0} }) } - #include "acpi/superio.asl" - -#ifdef ENABLE_TPM - Device (TPM) // Trusted Platform Module + Device (TPM) // Trusted Platform Module { - Name(_HID, EISAID("IFX0102")) - Name(_CID, 0x310cd041) - Name(_UID, 1) + Name (_HID, EISAID("IFX0102")) + Name (_CID, 0x310cd041) + Name (_UID, 1) - Method(_STA, 0) + Method (_STA, 0) { If (TPMP) { Return (0xf) + } Else { + Return (0x0) } - Return (0x0) } - Name(_CRS, ResourceTemplate() { + Name (_CRS, ResourceTemplate() { IO (Decode16, 0x2e, 0x2e, 0x01, 0x02) IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10) Memory32Fixed (ReadWrite, 0xfed40000, 0x5000) IRQ (Edge, Activehigh, Exclusive) { 6 } }) } -#endif + #include "gpio.asl" + #include "irqlinks.asl" + #include + #include } diff --git a/src/soc/intel/broadwell/acpi/pch.asl b/src/soc/intel/broadwell/acpi/pch.asl index 94e2ef9f53..c48449363e 100644 --- a/src/soc/intel/broadwell/acpi/pch.asl +++ b/src/soc/intel/broadwell/acpi/pch.asl @@ -18,17 +18,15 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* Intel Cougar Point PCH support */ #include -Scope(\) +Scope (\) { // IO-Trap at 0x800. This is the ACPI->SMI communication interface. - - OperationRegion(IO_T, SystemIO, 0x800, 0x10) - Field(IO_T, ByteAcc, NoLock, Preserve) + OperationRegion (IO_T, SystemIO, 0x800, 0x10) + Field (IO_T, ByteAcc, NoLock, Preserve) { - Offset(0x8), + Offset (0x8), TRP0, 8 // IO-Trap at 0x808 } @@ -36,39 +34,10 @@ Scope(\) OperationRegion (RCRB, SystemMemory, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) Field (RCRB, DWordAcc, Lock, Preserve) { - Offset(0x0000), // Backbone - Offset(0x1000), // Chipset - Offset(0x3000), // Legacy Configuration Registers - Offset(0x3404), // High Performance Timer Configuration + Offset (0x3404), // High Performance Timer Configuration HPAS, 2, // Address Select , 5, HPTE, 1, // Address Enable - Offset(0x3418), // FD (Function Disable) - , 1, // Reserved - PCID, 1, // PCI bridge disable - SA1D, 1, // SATA1 disable - SMBD, 1, // SMBUS disable - HDAD, 1, // Azalia disable - , 8, // Reserved - EH2D, 1, // EHCI #2 disable - LPBD, 1, // LPC bridge disable - EH1D, 1, // EHCI #1 disable - RP1D, 1, // Root Port 1 disable - RP2D, 1, // Root Port 2 disable - RP3D, 1, // Root Port 3 disable - RP4D, 1, // Root Port 4 disable - RP5D, 1, // Root Port 5 disable - RP6D, 1, // Root Port 6 disable - RP7D, 1, // Root Port 7 disable - RP8D, 1, // Root Port 8 disable - TTRD, 1, // Thermal sensor registers disable - SA2D, 1, // SATA2 disable - Offset(0x3428), // FD2 (Function Disable 2) - BDFD, 1, // Display BDF - ME1D, 1, // ME Interface 1 disable - ME2D, 1, // ME Interface 2 disable - IDRD, 1, // IDE redirect disable - KTCT, 1, // Keyboard Text redirect disable } } @@ -87,7 +56,7 @@ Scope(\) // LPC Bridge 0:1f.0 #include "lpc.asl" -// SATA 0:1f.2, 0:1f.5 +// SATA 0:1f.2 #include "sata.asl" // SMBus 0:1f.3 diff --git a/src/soc/intel/broadwell/acpi/pcie.asl b/src/soc/intel/broadwell/acpi/pcie.asl index a1f5f16d57..a48bdde0e3 100644 --- a/src/soc/intel/broadwell/acpi/pcie.asl +++ b/src/soc/intel/broadwell/acpi/pcie.asl @@ -18,9 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* Intel 6/7 Series PCH PCIe support */ - -// PCI Express Ports +/* Intel PCH PCIe support */ Method (IRQM, 1, Serialized) { diff --git a/src/soc/intel/broadwell/acpi/sata.asl b/src/soc/intel/broadwell/acpi/sata.asl index f8c0867aeb..0af2a3f3f5 100644 --- a/src/soc/intel/broadwell/acpi/sata.asl +++ b/src/soc/intel/broadwell/acpi/sata.asl @@ -19,64 +19,7 @@ */ // Intel SATA Controller 0:1f.2 - -// Note: Some BIOSes put the S-ATA code into an SSDT to make it easily -// pluggable - Device (SATA) { Name (_ADR, 0x001f0002) - - Device (PRID) - { - Name (_ADR, 0) - - // Get Timing Mode - Method (_GTM) - { - Name(PBUF, Buffer(20) { - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00 }) - - CreateDwordField (PBUF, 0, PIO0) - CreateDwordField (PBUF, 4, DMA0) - CreateDwordField (PBUF, 8, PIO1) - CreateDwordField (PBUF, 12, DMA1) - CreateDwordField (PBUF, 16, FLAG) - - // TODO fill return structure - - Return (PBUF) - } - - // Set Timing Mode - Method (_STM, 3) - { - CreateDwordField (Arg0, 0, PIO0) - CreateDwordField (Arg0, 4, DMA0) - CreateDwordField (Arg0, 8, PIO1) - CreateDwordField (Arg0, 12, DMA1) - CreateDwordField (Arg0, 16, FLAG) - - // TODO: Do the deed - } - - Device (DSK0) - { - Name (_ADR, 0) - // TODO: _RMV ? - // TODO: _GTF ? - } - - Device (DSK1) - { - Name (_ADR, 1) - - // TODO: _RMV ? - // TODO: _GTF ? - } - - } } - diff --git a/src/soc/intel/broadwell/acpi/sleepstates.asl b/src/soc/intel/broadwell/acpi/sleepstates.asl index ec185d21ee..6fea862d86 100644 --- a/src/soc/intel/broadwell/acpi/sleepstates.asl +++ b/src/soc/intel/broadwell/acpi/sleepstates.asl @@ -18,9 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -Name(\_S0, Package(){0x0,0x0,0x0,0x0}) -// Name(\_S1, Package(){0x1,0x1,0x0,0x0}) -Name(\_S3, Package(){0x5,0x5,0x0,0x0}) -Name(\_S4, Package(){0x6,0x6,0x0,0x0}) -Name(\_S5, Package(){0x7,0x7,0x0,0x0}) - +Name (\_S0, Package () { 0x0, 0x0, 0x0, 0x0 }) +Name (\_S1, Package () { 0x1, 0x1, 0x0, 0x0 }) +Name (\_S2, Package () { 0x1, 0x1, 0x0, 0x0 }) +Name (\_S3, Package () { 0x5, 0x5, 0x0, 0x0 }) +Name (\_S4, Package () { 0x6, 0x6, 0x0, 0x0 }) +Name (\_S5, Package () { 0x7, 0x7, 0x0, 0x0 }) diff --git a/src/soc/intel/broadwell/acpi/systemagent.asl b/src/soc/intel/broadwell/acpi/systemagent.asl index 99972a9c35..9c6dacd384 100644 --- a/src/soc/intel/broadwell/acpi/systemagent.asl +++ b/src/soc/intel/broadwell/acpi/systemagent.asl @@ -20,83 +20,23 @@ #include -Name(_HID,EISAID("PNP0A08")) // PCIe -Name(_CID,EISAID("PNP0A03")) // PCI +Name (_HID, EISAID ("PNP0A08")) // PCIe +Name (_CID, EISAID ("PNP0A03")) // PCI -Name(_ADR, 0) -Name(_BBN, 0) +Name (_ADR, 0) +Name (_BBN, 0) Device (MCHC) { - Name(_ADR, 0x00000000) // 0:0.0 + Name (_ADR, 0x00000000) // 0:0.0 - OperationRegion(MCHP, PCI_Config, 0x00, 0x100) + OperationRegion (MCHP, PCI_Config, 0x00, 0x100) Field (MCHP, DWordAcc, NoLock, Preserve) { - Offset (0x40), // EPBAR - EPEN, 1, // Enable - , 11, // - EPBR, 24, // EPBAR - - Offset (0x48), // MCHBAR - MHEN, 1, // Enable - , 13, // - MHBR, 22, // MCHBAR - - Offset (0x60), // PCIe BAR - PXEN, 1, // Enable - PXSZ, 2, // BAR size - , 23, // - PXBR, 10, // PCIe BAR - - Offset (0x68), // DMIBAR - DMEN, 1, // Enable - , 11, // - DMBR, 24, // DMIBAR - Offset (0x70), // ME Base Address MEBA, 64, - - // ... - - Offset (0x80), // PAM0 - , 4, - PM0H, 2, - , 2, - Offset (0x81), // PAM1 - PM1L, 2, - , 2, - PM1H, 2, - , 2, - Offset (0x82), // PAM2 - PM2L, 2, - , 2, - PM2H, 2, - , 2, - Offset (0x83), // PAM3 - PM3L, 2, - , 2, - PM3H, 2, - , 2, - Offset (0x84), // PAM4 - PM4L, 2, - , 2, - PM4H, 2, - , 2, - Offset (0x85), // PAM5 - PM5L, 2, - , 2, - PM5H, 2, - , 2, - Offset (0x86), // PAM6 - PM6L, 2, - , 2, - PM6H, 2, - , 2, - Offset (0xa0), // Top of Used Memory TOM, 64, - Offset (0xbc), // Top of Low Used Memory TLUD, 32, } @@ -242,8 +182,6 @@ Method (_CRS, 0, Serialized) Return (MCRS) } -/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ -#include "acpi/haswell_pci_irqs.asl" /* PCI Device Resource Consumption */ Device (PDRC) { @@ -267,6 +205,8 @@ Device (PDRC) } } +/* PCI IRQ assignment */ +#include "pci_irqs.asl" /* Configurable TDP */ #include "ctdp.asl"