From bb85775d920c3229bf4ca11daad17fb99f9330e7 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 16 Dec 2024 11:15:06 +0530 Subject: [PATCH] soc/intel/cmn/acpi: Add ACPI method to get LGMR address This patch adds an ACPI method to get the LPC Generic Memory Range (LGMR) address. This is necessary for platforms that need to access the LGMR from OS driver. The new method, called GLGM, reads the LGMR address from the LPC PCI configuration space (offset 0x98) and returns it as a 32-bit value. BUG=b:354066052 TEST=Able to build and boot google/brox. Change-Id: I4322cee2c608e550e233c45c68958e8a4046c361 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/85602 Reviewed-by: Kapil Porwal Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/acpi/acpi/lpc.asl | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/soc/intel/common/block/acpi/acpi/lpc.asl b/src/soc/intel/common/block/acpi/acpi/lpc.asl index c4a7dd3aaf..3e8f5a5ea0 100644 --- a/src/soc/intel/common/block/acpi/acpi/lpc.asl +++ b/src/soc/intel/common/block/acpi/acpi/lpc.asl @@ -9,6 +9,22 @@ Device (LPCB) Name (_ADR, 0x001f0000) Name (_DDN, "LPC Bus Device") + OperationRegion (LPCP, PCI_Config, 0x00, 0x100) + Field (LPCP, DWordAcc, NoLock, Preserve) + { + Offset(0x98), /* LGMR */ + LGEN, 1, /* Enable */ + , 15, + LADR, 16, /* MADDR [31:16] */ + } + + /* Get LGMR */ + Method (GLGM, 0, Serialized) + { + Local0 = LADR << 16 + Return (Local0) + } + /* DMA Controller */ Device (DMAC) {