From bb299bb530f1bd01e346f6ba6cd6f59b2bacb7cc Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 23 Jan 2026 12:20:11 -0600 Subject: [PATCH] mb/starlabs/starfighter/mtl: Add detection delay to PCH-attached SSD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some SSDs connected to the PCH-attached PCIe root port/m.2 socket need a small delay in order to be reliably detected. Add a 15ms delay (the default is 0) to ensure this. TEST=build/boot Starfighter MTL 125H/285H with Samsung 970 EVO plus, WD SN720, and Intel Optane P1600x SSDs in outer SSD socket. Ensure all drives detected and bootable after both cold and warm resets. Change-Id: I16ec0a313fc7cccb2807593c07db04cdbb59c979 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/90880 Reviewed-by: Paul Menzel Reviewed-by: Jérémy Compostella Tested-by: build bot (Jenkins) Reviewed-by: Sean Rhodes --- src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb index f83df3e27a..23ad639cc2 100644 --- a/src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb +++ b/src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb @@ -241,6 +241,7 @@ chip soc/intel/meteorlake .flags = PCIE_RP_LTR | PCIE_RP_AER, .pcie_rp_aspm = ASPM_L0S_L1, .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_detect_timeout_ms = 15, }" smbios_slot_desc "SlotTypeM2Socket3"