From baf28f86686984c54e33871faa851669fe94b7a0 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Thu, 26 Jun 2025 10:20:52 +0800
Subject: [PATCH] mb/trulo/var/pujjolo: Add GPE configuration

Follow baseboard nissa and project pujjocento project to setting
GPE configuration.

BUG=b:395763555
BRANCH=none
TEST=Build and boot to OS.

Change-Id: I75deadd0c1b7218c2d0820d637cc2ec02bf9154f
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88199
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/pujjolo/overridetree.cb | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 3fca8c3d8f..9fbff83aa2 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -23,6 +23,11 @@ fw_config
 end
 chip soc/intel/alderlake
 
+	# GPE configuration
+	register "pmc_gpe0_dw0" = "GPP_A"
+	register "pmc_gpe0_dw1" = "GPP_H"
+	register "pmc_gpe0_dw2" = "GPP_F"
+
 	# S0ix enable
 	register "s0ix_enable" = "true"