diff --git a/src/mainboard/starlabs/adl/Kconfig b/src/mainboard/starlabs/adl/Kconfig
index b39f9c914d..479ec79165 100644
--- a/src/mainboard/starlabs/adl/Kconfig
+++ b/src/mainboard/starlabs/adl/Kconfig
@@ -19,6 +19,7 @@ config BOARD_STARLABS_ADL_SERIES
 	select SOC_INTEL_CRASHLOG
 	select SPD_READ_BY_WORD
 	select SPI_FLASH_WINBOND
+	select STARLABS_NVME_POWER_SEQUENCE
 	select TPM2
 	select VALIDATE_INTEL_DESCRIPTOR
 
diff --git a/src/mainboard/starlabs/adl/mainboard.c b/src/mainboard/starlabs/adl/mainboard.c
index f8c9aea3ae..940584b151 100644
--- a/src/mainboard/starlabs/adl/mainboard.c
+++ b/src/mainboard/starlabs/adl/mainboard.c
@@ -1,11 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <bootstate.h>
 #include <device/device.h>
 #include <drivers/intel/gma/opregion.h>
 #include <soc/ramstage.h>
 #include <variants.h>
 
-static void init_mainboard(void *chip_info)
+static void starlabs_configure_mainboard(void *unused)
 {
 	const struct pad_config *pads;
 	size_t num;
@@ -16,6 +17,8 @@ static void init_mainboard(void *chip_info)
 	devtree_update();
 }
 
+BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, starlabs_configure_mainboard, NULL);
+
 void __weak starlabs_adl_mainboard_fill_ssdt(const struct device *dev)
 {
 	(void)dev;
@@ -27,6 +30,5 @@ static void enable_mainboard(struct device *dev)
 }
 
 struct chip_operations mainboard_ops = {
-	.init = init_mainboard,
 	.enable_dev = enable_mainboard,
 };
diff --git a/src/mainboard/starlabs/adl/variants/hz/gpio.c b/src/mainboard/starlabs/adl/variants/hz/gpio.c
index e214a14cec..4cb0af527d 100644
--- a/src/mainboard/starlabs/adl/variants/hz/gpio.c
+++ b/src/mainboard/starlabs/adl/variants/hz/gpio.c
@@ -1,12 +1,42 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <variants.h>
+#include <common/nvme_seq.h>
+
+#if ENV_RAMSTAGE
+static const struct pad_config nvme_pads[] = {
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),				/* Enable */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),			/* Clock Request 0 */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),				/* Reset asserted */
+};
+
+static const struct pad_config post_nvme_pads[] = {
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST),				/* Reset deasserted */
+};
+
+const struct pad_config *variant_nvme_power_sequence_pads(size_t *num)
+{
+	*num = ARRAY_SIZE(nvme_pads);
+	return nvme_pads;
+}
+
+const struct pad_config *variant_nvme_power_sequence_post_pads(size_t *num)
+{
+	*num = ARRAY_SIZE(post_nvme_pads);
+	return post_nvme_pads;
+}
+#endif
 
 /* Early pad configuration in bootblock */
 const struct pad_config early_gpio_table[] = {
 	/* Debug Connector */
 	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),				/* RXD */
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),				/* TXD */
+
+	/* SSD */
+	PAD_CFG_GPI(GPP_D5, NONE, DEEP),					/* Clock Request 0 */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),					/* Reset asserted */
+	PAD_CFG_GPO(GPP_D16, 0, DEEP),					/* Enable (PWREN off) */
 };
 
 const struct pad_config *variant_early_gpio_table(size_t *num)
@@ -40,9 +70,9 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_APIC_LOW(GPP_E12, NONE, PLTRST),			/* Interrupt */
 
 	/* SSD */
-	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),				/* Clock Request 0 */
-	PAD_CFG_GPO(GPP_H0, 1, PLTRST),					/* Reset */
-	PAD_CFG_GPO(GPP_D16, 1, DEEP),					/* Enable */
+	PAD_NC(GPP_D5, NONE),						/* Clock Request 0 */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),					/* Reset asserted */
+	PAD_CFG_GPO(GPP_D16, 0, DEEP),					/* Enable (PWREN off) */
 
 	/* Wireless */
 	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),				/* BRI Data */
diff --git a/src/mainboard/starlabs/adl/variants/i5/gpio.c b/src/mainboard/starlabs/adl/variants/i5/gpio.c
index e6c03fd9c0..12b61daf05 100644
--- a/src/mainboard/starlabs/adl/variants/i5/gpio.c
+++ b/src/mainboard/starlabs/adl/variants/i5/gpio.c
@@ -1,12 +1,42 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <variants.h>
+#include <common/nvme_seq.h>
+
+#if ENV_RAMSTAGE
+static const struct pad_config nvme_pads[] = {
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),       /* Enable */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* Clock Request 0 */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),      /* Reset asserted */
+};
+
+static const struct pad_config post_nvme_pads[] = {
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST), /* Reset deasserted */
+};
+
+const struct pad_config *variant_nvme_power_sequence_pads(size_t *num)
+{
+	*num = ARRAY_SIZE(nvme_pads);
+	return nvme_pads;
+}
+
+const struct pad_config *variant_nvme_power_sequence_post_pads(size_t *num)
+{
+	*num = ARRAY_SIZE(post_nvme_pads);
+	return post_nvme_pads;
+}
+#endif
 
 /* Early pad configuration in bootblock */
 const struct pad_config early_gpio_table[] = {
 	/* Debug Connector */
 	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* RXD */
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* TXD */
+
+	/* SSD */
+	PAD_CFG_GPI(GPP_D5, NONE, DEEP), /* Clock Request 0 */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),  /* Reset asserted */
+	PAD_CFG_GPO(GPP_D16, 0, DEEP),   /* Enable (PWREN off) */
 };
 
 const struct pad_config *variant_early_gpio_table(size_t *num)
@@ -49,9 +79,9 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_SMI_LOW(GPP_F15, NONE, DEEP, EDGE_BOTH), /* Detect */
 
 	/* SSD */
-	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* Clock Request 0 */
-	PAD_CFG_GPO(GPP_H0, 1, PLTRST),      /* Reset */
-	PAD_CFG_GPO(GPP_D16, 1, DEEP),       /* Enable */
+	PAD_NC(GPP_D5, NONE),                /* Clock Request 0 */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),      /* Reset asserted */
+	PAD_CFG_GPO(GPP_D16, 0, DEEP),       /* Enable (PWREN off) */
 
 	/* Wireless */
 	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),   /* BRI Data */
diff --git a/src/mainboard/starlabs/adl/variants/y2/gpio.c b/src/mainboard/starlabs/adl/variants/y2/gpio.c
index 12d9bcb472..849daadd57 100644
--- a/src/mainboard/starlabs/adl/variants/y2/gpio.c
+++ b/src/mainboard/starlabs/adl/variants/y2/gpio.c
@@ -1,12 +1,42 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <variants.h>
+#include <common/nvme_seq.h>
+
+#if ENV_RAMSTAGE
+static const struct pad_config nvme_pads[] = {
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),				/* Enable */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),			/* Clock Request 0 */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),				/* Reset asserted */
+};
+
+static const struct pad_config post_nvme_pads[] = {
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST),				/* Reset deasserted */
+};
+
+const struct pad_config *variant_nvme_power_sequence_pads(size_t *num)
+{
+	*num = ARRAY_SIZE(nvme_pads);
+	return nvme_pads;
+}
+
+const struct pad_config *variant_nvme_power_sequence_post_pads(size_t *num)
+{
+	*num = ARRAY_SIZE(post_nvme_pads);
+	return post_nvme_pads;
+}
+#endif
 
 /* Early pad configuration in bootblock */
 const struct pad_config early_gpio_table[] = {
 	/* Debug Connector */
 	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),				/* RXD */
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),				/* TXD */
+
+	/* SSD */
+	PAD_CFG_GPI(GPP_D5, NONE, DEEP),					/* Clock Request 0 */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),					/* Reset asserted */
+	PAD_CFG_GPO(GPP_D16, 0, DEEP),					/* Enable (PWREN off) */
 };
 
 const struct pad_config *variant_early_gpio_table(size_t *num)
@@ -36,9 +66,9 @@ const struct pad_config gpio_table[] = {
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A10, NONE, DEEP, NF1),	/* eSPI Reset */
 
 	/* SSD */
-	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),				/* Clock Request 0 */
-	PAD_CFG_GPO(GPP_H0, 1, PLTRST),					/* Reset */
-	PAD_CFG_GPO(GPP_D16, 1, DEEP),					/* Enable */
+	PAD_NC(GPP_D5, NONE),						/* Clock Request 0 */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),					/* Reset asserted */
+	PAD_CFG_GPO(GPP_D16, 0, DEEP),					/* Enable (PWREN off) */
 	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5),				/* Device Sleep */
 	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),				/* PEDET */