soc/intel: Add Arrow Lake-H/U IDs
Add IDs from the EDS, with a couple extras: - eSPI: EDS says 0x7202, but our boards show 0x7702 - GT: Value changes between 0x7d51 and 0x7dd1 based on DIMMs installed Change-Id: I8430914edd02954cbb38592bff896733b01c735d Ref: Intel Arrow Lake-H/U EDS, Volume 1 (#777369, rev 2.0) Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87131 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Jeremy Soller
Felix Singer
parent
3e1f96a0f4
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ba8407f0c1
26 changed files with 104 additions and 0 deletions
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@ -2182,6 +2182,7 @@
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#define PCI_DID_INTEL_TGL_ISHB 0xa0fc
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#define PCI_DID_INTEL_TGL_H_ISHB 0x43fc
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#define PCI_DID_INTEL_MTL_ISHB 0x7e45
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#define PCI_DID_INTEL_ARL_ISHB 0x7745
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#define PCI_DID_INTEL_ADL_N_ISHB 0x54fc
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#define PCI_DID_INTEL_ADL_P_ISHB 0x51fc
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#define PCI_DID_INTEL_LNL_ISHB 0xa845
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@ -3142,6 +3143,9 @@
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#define PCI_DID_INTEL_MTL_ESPI_5 0x7e05
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#define PCI_DID_INTEL_MTL_ESPI_6 0x7e06
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#define PCI_DID_INTEL_MTL_ESPI_7 0x7e07
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#define PCI_DID_INTEL_ARL_H_ESPI_0 0x7202
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#define PCI_DID_INTEL_ARL_H_ESPI_1 0x7702
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#define PCI_DID_INTEL_ARL_U_ESPI_0 0x7203
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#define PCI_DID_INTEL_RPP_P_ESPI_0 0x5180
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#define PCI_DID_INTEL_RPP_P_ADP_P_ESPI_1 0x5181
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#define PCI_DID_INTEL_RPP_P_ADP_P_ESPI_2 0x5182
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@ -3637,6 +3641,16 @@
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#define PCI_DID_INTEL_MTL_IOE_P_PCIE_RP11 0x7ecb
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#define PCI_DID_INTEL_MTL_IOE_P_PCIE_RP12 0x7ecc
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#define PCI_DID_INTEL_ARL_SOC_PCIE_RP1 0x7738
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#define PCI_DID_INTEL_ARL_SOC_PCIE_RP2 0x7739
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#define PCI_DID_INTEL_ARL_SOC_PCIE_RP3 0x773a
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#define PCI_DID_INTEL_ARL_SOC_PCIE_RP4 0x773b
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#define PCI_DID_INTEL_ARL_SOC_PCIE_RP5 0x773c
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#define PCI_DID_INTEL_ARL_SOC_PCIE_RP6 0x773d
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#define PCI_DID_INTEL_ARL_SOC_PCIE_RP7 0x773e
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#define PCI_DID_INTEL_ARL_SOC_PCIE_RP8 0x773f
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#define PCI_DID_INTEL_ARL_SOC_PCIE_RP9 0x774d
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#define PCI_DID_INTEL_RPL_P_PCIE_RP1 0xa74d
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#define PCI_DID_INTEL_RPL_P_PCIE_RP2 0xa70d
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#define PCI_DID_INTEL_RPL_P_PCIE_RP3 0xa72d
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@ -3805,6 +3819,7 @@
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#define PCI_DID_INTEL_ADP_M_SATA_2 0x54d7
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#define PCI_DID_INTEL_ADP_M_SATA_3 0x282a
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#define PCI_DID_INTEL_MTL_SATA 0x7e63
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#define PCI_DID_INTEL_ARL_SATA 0x7763
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#define PCI_DID_INTEL_RPP_P_SATA_1 0x51d3
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#define PCI_DID_INTEL_RPP_P_SATA_2 0x51d7
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#define PCI_DID_INTEL_RPP_S_SATA 0x7a62
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@ -3834,6 +3849,7 @@
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#define PCI_DID_INTEL_MTL_SOC_PMC 0x7e21
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#define PCI_DID_INTEL_MTL_IOE_M_PMC 0x7ebe
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#define PCI_DID_INTEL_MTL_IOE_P_PMC 0x7ece
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#define PCI_DID_INTEL_ARL_SOC_PMC 0x7721
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#define PCI_DID_INTEL_RPP_P_PMC 0x51a1
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#define PCI_DID_INTEL_RPP_S_PMC 0x7a21
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#define PCI_DID_INTEL_LNL_PMC 0xa821
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@ -3964,6 +3980,13 @@
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#define PCI_DID_INTEL_MTL_I2C4 0x7e50
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#define PCI_DID_INTEL_MTL_I2C5 0x7e51
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#define PCI_DID_INTEL_ARL_I2C0 0x7778
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#define PCI_DID_INTEL_ARL_I2C1 0x7779
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#define PCI_DID_INTEL_ARL_I2C2 0x777A
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#define PCI_DID_INTEL_ARL_I2C3 0x777B
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#define PCI_DID_INTEL_ARL_I2C4 0x7750
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#define PCI_DID_INTEL_ARL_I2C5 0x7751
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#define PCI_DID_INTEL_LNL_I2C0 0xa878
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#define PCI_DID_INTEL_LNL_I2C1 0xa879
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#define PCI_DID_INTEL_LNL_I2C2 0xa87a
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@ -4070,6 +4093,10 @@
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#define PCI_DID_INTEL_MTL_UART1 0x7e26
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#define PCI_DID_INTEL_MTL_UART2 0x7e52
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#define PCI_DID_INTEL_ARL_UART0 0x7725
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#define PCI_DID_INTEL_ARL_UART1 0x7726
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#define PCI_DID_INTEL_ARL_UART2 0x7752
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#define PCI_DID_INTEL_LNL_UART0 0xa825
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#define PCI_DID_INTEL_LNL_UART1 0xa826
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#define PCI_DID_INTEL_LNL_UART2 0xa852
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@ -4179,6 +4206,11 @@
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#define PCI_DID_INTEL_MTL_GSPI1 0x7e30
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#define PCI_DID_INTEL_MTL_GSPI2 0x7e46
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#define PCI_DID_INTEL_ARL_HWSEQ_SPI 0x7723
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#define PCI_DID_INTEL_ARL_GSPI0 0x7727
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#define PCI_DID_INTEL_ARL_GSPI1 0x7730
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#define PCI_DID_INTEL_ARL_GSPI2 0x7746
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#define PCI_DID_INTEL_LNL_HWSEQ_SPI 0xa823
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#define PCI_DID_INTEL_LNL_GSPI0 0xa827
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#define PCI_DID_INTEL_LNL_GSPI1 0xa830
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@ -4342,6 +4374,8 @@
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#define PCI_DID_INTEL_MTL_P_GT2_3 0x7d55
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#define PCI_DID_INTEL_MTL_P_GT2_4 0x7d60
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#define PCI_DID_INTEL_MTL_P_GT2_5 0x7dd5
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#define PCI_DID_INTEL_ARL_H_GT2_1 0x7d51
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#define PCI_DID_INTEL_ARL_H_GT2_2 0x7dd1
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#define PCI_DID_INTEL_RPL_HX_GT1 0xa788
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#define PCI_DID_INTEL_RPL_HX_GT2 0xa78b
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#define PCI_DID_INTEL_RPL_HX_GT3 0x4688
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@ -4496,6 +4530,8 @@
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#define PCI_DID_INTEL_MTL_P_ID_3 0x7d14
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#define PCI_DID_INTEL_MTL_P_ID_4 0x7d15
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#define PCI_DID_INTEL_MTL_P_ID_5 0x7d16
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#define PCI_DID_INTEL_ARL_H_ID_1 0x7d06
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#define PCI_DID_INTEL_ARL_H_ID_2 0x7d20
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#define PCI_DID_INTEL_RPL_HX_ID_1 0xa702
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#define PCI_DID_INTEL_RPL_HX_ID_2 0xa729
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#define PCI_DID_INTEL_RPL_HX_ID_3 0xa728
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@ -4553,6 +4589,7 @@
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#define PCI_DID_INTEL_ADP_S_SMBUS 0x7aa3
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#define PCI_DID_INTEL_ADP_M_N_SMBUS 0x54a3
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#define PCI_DID_INTEL_MTL_SMBUS 0x7e22
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#define PCI_DID_INTEL_ARL_SMBUS 0x7722
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#define PCI_DID_INTEL_RPP_P_SMBUS 0x51a3
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#define PCI_DID_INTEL_RPP_S_SMBUS 0x7a23
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#define PCI_DID_INTEL_LNL_SMBUS 0xa822
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@ -4597,6 +4634,7 @@
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#define PCI_DID_INTEL_MTL_XHCI 0x7e7d
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#define PCI_DID_INTEL_MTL_M_TCSS_XHCI 0x7eb0
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#define PCI_DID_INTEL_MTL_P_TCSS_XHCI 0x7ec0
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#define PCI_DID_INTEL_ARL_XHCI 0x777d
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#define PCI_DID_INTEL_RPP_P_TCSS_XHCI 0xa71e
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#define PCI_DID_INTEL_RPP_S_XHCI 0x7a60
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#define PCI_DID_INTEL_LNL_XHCI 0xa87d
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@ -4632,6 +4670,7 @@
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#define PCI_DID_INTEL_MTL_SOC_P2SB 0x7e20
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#define PCI_DID_INTEL_MTL_IOE_M_P2SB 0x7eb8
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#define PCI_DID_INTEL_MTL_IOE_P_P2SB 0x7ec8
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#define PCI_DID_INTEL_ARL_SOC_P2SB 0x7720
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#define PCI_DID_INTEL_RPP_P_P2SB 0x51a0
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#define PCI_DID_INTEL_RPP_S_P2SB 0x7a20
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#define PCI_DID_INTEL_LNL_P2SB 0xa820
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@ -4657,6 +4696,7 @@
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#define PCI_DID_INTEL_MTL_SOC_SRAM 0x7e7f
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#define PCI_DID_INTEL_MTL_IOE_M_SRAM 0x7ebf
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#define PCI_DID_INTEL_MTL_IOE_P_SRAM 0x7ecf
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#define PCI_DID_INTEL_ARL_SOC_SRAM 0x777f
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#define PCI_DID_INTEL_LNL_SRAM 0xa87f
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#define PCI_DID_INTEL_PTL_H_SRAM 0xe47f
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#define PCI_DID_INTEL_PTL_U_H_SRAM 0xe37f
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@ -4718,6 +4758,8 @@
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#define PCI_DID_INTEL_MTL_AUDIO_7 0x7e2e
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#define PCI_DID_INTEL_MTL_AUDIO_8 0x7e2f
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#define PCI_DID_INTEL_ARL_AUDIO 0x7728
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#define PCI_DID_INTEL_LNL_AUDIO_1 0xa828
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#define PCI_DID_INTEL_LNL_AUDIO_2 0xa829
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#define PCI_DID_INTEL_LNL_AUDIO_3 0xa82a
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@ -4797,6 +4839,7 @@
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#define PCI_DID_INTEL_RPP_S_CSE2 0x7a6c
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#define PCI_DID_INTEL_RPP_S_CSE3 0x7a6d
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#define PCI_DID_INTEL_MTL_CSE0 0x7e70
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#define PCI_DID_INTEL_ARL_CSE0 0x7770
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#define PCI_DID_INTEL_LNL_CSE0 0xa870
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#define PCI_DID_INTEL_PTL_H_CSE0 0xe470
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#define PCI_DID_INTEL_PTL_U_H_CSE0 0xe370
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@ -4825,6 +4868,7 @@
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#define PCI_DID_INTEL_MTL_XDCI 0x7e7e
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#define PCI_DID_INTEL_MTL_M_TCSS_XDCI 0x7eb1
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#define PCI_DID_INTEL_MTL_P_TCSS_XDCI 0x7ec1
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#define PCI_DID_INTEL_ARL_XDCI 0x777e
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#define PCI_DID_INTEL_PTL_H_XDCI 0xe47e
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#define PCI_DID_INTEL_PTL_U_H_XDCI 0xe37e
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#define PCI_DID_INTEL_WCL_XDCI 0x4d7e
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@ -4983,6 +5027,7 @@
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#define PCI_DID_INTEL_MTL_CNVI_WIFI_1 0x7e41
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#define PCI_DID_INTEL_MTL_CNVI_WIFI_2 0x7e42
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#define PCI_DID_INTEL_MTL_CNVI_WIFI_3 0x7e43
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#define PCI_DID_INTEL_ARL_CNVI_WIFI 0x7740
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#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_0 0x7a70
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#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_1 0x7a71
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#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_2 0x7a72
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@ -5034,6 +5079,7 @@
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/* Intel Trace Hub */
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#define PCI_DID_INTEL_MTL_TRACEHUB 0x7e24
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#define PCI_DID_INTEL_ARL_TRACEHUB 0x7724
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#define PCI_DID_INTEL_RPL_TRACEHUB 0xa76f
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#define PCI_DID_INTEL_PTL_H_TRACEHUB 0xe424
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#define PCI_DID_INTEL_PTL_U_H_TRACEHUB 0xe324
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@ -5061,6 +5107,10 @@
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#define PCI_DID_INTEL_WCL_THC0_SPI 0x4d49
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#define PCI_DID_INTEL_WCL_THC1_I2C 0x4d4a
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#define PCI_DID_INTEL_WCL_THC1_SPI 0x4d4b
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#define PCI_DID_INTEL_ARL_THC0_1 0x7748
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#define PCI_DID_INTEL_ARL_THC0_2 0x7749
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#define PCI_DID_INTEL_ARL_THC1_1 0x774a
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#define PCI_DID_INTEL_ARL_THC1_2 0x774b
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#define PCI_VID_COMPUTONE 0x8e0e
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#define PCI_DID_COMPUTONE_IP2EX 0x0291
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