erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

UPSTREAM: cpu/intel: Add MSR to support enabling turbo frequency

Browse source 
This patch adds definition FREQ_LIMIT_RATIO MSR. FREQ_LIMIT_RATIO
register allows to determine the ratio limits to be used to limit
frequency.

BUG=chrome-os-partner:58158
BRANCH=None
TEST=None

Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/17211
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I50a792accbaab1bff313fd00574814d7dbba1f6b
Reviewed-on: https://chromium-review.googlesource.com/410079
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Shaunak Saha 2016-11-02 10:52:23 -07:00 • committed by chrome-bot
commit b9d70b02ba
1 changed files with 1 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/include/cpu/intel/speedstep.h
View file

@ -46,7 +46,7 @@
#define MSR_PMG_IO_BASE_ADDR 0xe3
#define MSR_PMG_IO_CAPTURE_ADDR 0xe4
#define MSR_EXTENDED_CONFIG 0xee
#define FREQ_LIMIT_RATIO 0x1AD
typedef struct {
uint8_t dynfsb : 1; /* whether this is SLFM */