From b94c8c715febe3a04bfdf52f7b69d73ece0f6faf Mon Sep 17 00:00:00 2001 From: Kenji Chen Date: Fri, 10 Oct 2014 03:08:15 +0800 Subject: [PATCH] Broadwell: Select PCIE_L1_SUB_STATE and apply Broadwell settings. BUG=chrome-os-partner:31424 TEST=Build an image and confirm the settings are correctly applied to registers for PCIe L1 Sub-State feature enabling. Signed-off-by: Kenji Chen Change-Id: I07ce6eea648b1b37d606f5529edad184e3de70ac Reviewed-on: https://chromium-review.googlesource.com/222599 Reviewed-by: Duncan Laurie --- src/soc/intel/broadwell/Kconfig | 1 + src/soc/intel/broadwell/pcie.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index b898bd90be..13953e5710 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -35,6 +35,7 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select PCIEXP_CLK_PM + select PCIEXP_L1_SUB_STATE select SMM_MODULES select SMM_TSEG select SMP diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index bccb2c47c6..8b14f5b509 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -654,8 +654,15 @@ static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) pci_write_config32(dev, 0x94, (device << 16) | vendor); } +static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int off) +{ + /* Set max snoop and non-snoop latency for Broadwell */ + pci_mmio_write_config32(dev, off, 0x10031003); +} + static struct pci_operations pcie_ops = { .set_subsystem = pcie_set_subsystem, + .set_L1_ss_latency = pcie_set_L1_ss_max_latency, }; static struct device_operations device_ops = {