From b93bc06de76cab0a1ec9a56e12c9a6942a430893 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 21 Nov 2014 17:04:42 -0800 Subject: [PATCH] t132: Change memlayout to have PRERAM and POSTRAM CBFS Cache Instead of having unified CBFS_CACHE and limiting the POSTRAM Cache size, split them into PRERAM and POSTRAM CBFS_CACHE. BUG=None BRANCH=None TEST=Compiles successfully for both rush and ryu. Boots to kernel prompt on ryu. Signed-off-by: Furquan Shaikh Change-Id: Iab21ff5c7ca880b6bd18846e5d8d71c26dff56cf Reviewed-on: https://chromium-review.googlesource.com/231546 Reviewed-by: Aaron Durbin Tested-by: Furquan Shaikh Commit-Queue: Furquan Shaikh --- src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld index 0de1d71dd5..1d9db2614d 100644 --- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld @@ -33,7 +33,7 @@ SECTIONS { SRAM_START(0x40000000) PRERAM_CBMEM_CONSOLE(0x40000000, 8K) - CBFS_CACHE(0x40002000, 72K) + PRERAM_CBFS_CACHE(0x40002000, 72K) VBOOT2_WORK(0x40014000, 16K) STACK(0x40018000, 2K) TIMESTAMP(0x40018800, 2K) @@ -43,5 +43,6 @@ SECTIONS SRAM_END(0x40040000) DRAM_START(0x80000000) + POSTRAM_CBFS_CACHE(0x80100000, 1M) RAMSTAGE(0x80200000, 256K) }