t132: Add timestamp collection support in t132

Add a region TIMESTAMP to store all the timestamps starting from bootblock to
end of romstage. At the end of romstage take all the timestamps in TIMESTAMP
region and put it into cbmem

BUG=chrome-os-partner:32973
BRANCH=None
TEST=Compiles successfully and cbmem -t prints all timestamps

Change-Id: I856564de80589bede660ca6bc1275193f8a2fa4b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/223110
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>

src/soc/nvidia/tegra132/Kconfig

@@ -17,6 +17,8 @@ config SOC_NVIDIA_TEGRA132
 	select DYNAMIC_CBMEM
 	select SMP
 	select ARCH_USE_SECURE_MONITOR
+	select COLLECT_TIMESTAMPS
+	select HAS_PRECBMEM_TIMESTAMP_REGION
 
 if SOC_NVIDIA_TEGRA132
 

src/soc/nvidia/tegra132/bootblock.c

@@ -28,6 +28,7 @@
 #include <soc/nvidia/tegra/apbmisc.h>
 #include <soc/pmc.h>
 #include <soc/power.h>
+#include <timestamp.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 #define BCT_OFFSET_IN_BIT	0x50
@@ -62,6 +63,9 @@ void main(void)
 {
 	void *entry = NULL;
 
+	timestamp_early_init(0);
+	timestamp_add_now(TS_START_BOOTBLOCK);
+
 	// enable JTAG at the earliest stage
 	enable_jtag();
 
@@ -106,6 +110,8 @@ void main(void)
 		printk(BIOS_INFO, "T132 bootblock: jumping to romstage\n");
 	}
 
+	timestamp_add_now(TS_END_BOOTBLOCK);
+
 	if (entry != CBFS_LOAD_ERROR)
 		stage_exit(entry);
 	else

src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld

@@ -35,7 +35,8 @@ SECTIONS
 	PRERAM_CBMEM_CONSOLE(0x40000000, 8K)
 	CBFS_CACHE(0x40002000, 72K)
 	VBOOT2_WORK(0x40014000, 16K)
-	STACK(0x40018000, 8K)
+	STACK(0x40018000, 4K)
+	TIMESTAMP(0x40019000, 4K)
 	BOOTBLOCK(0x4001A000, 20K)
 	VERSTAGE(0x4001F000, 60K)
 	ROMSTAGE(0x4002E000, 72K)

src/soc/nvidia/tegra132/romstage.c

@@ -29,6 +29,7 @@
 #include <soc/sdram_configs.h>
 #include <soc/romstage.h>
 #include <timer.h>
+#include <timestamp.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 void __attribute__((weak)) romstage_mainboard_init(void)
@@ -43,6 +44,8 @@ static void *load_ramstage(void)
 
 	stopwatch_init(&sw);
 
+	timestamp_add_now(TS_START_COPYRAM);
+
 #if IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)
 	entry = vboot2_load_ramstage();
 #else
@@ -58,6 +61,8 @@ static void *load_ramstage(void)
 		entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
 					CONFIG_CBFS_PREFIX "/ramstage");
 
+	timestamp_add_now(TS_END_COPYRAM);
+
 	printk(BIOS_DEBUG, "Ramstage load time: %ld usecs.\n",
 		stopwatch_duration_usecs(&sw));
 
@@ -68,11 +73,15 @@ void romstage(void)
 {
 	void *entry;
 
+	timestamp_add_now(TS_START_ROMSTAGE);
+
 	console_init();
 	exception_init();
 
 	printk(BIOS_INFO, "T132: romstage here\n");
 
+	timestamp_add_now(TS_BEFORE_INITRAM);
+
 #if CONFIG_BOOTROM_SDRAM_INIT
 	printk(BIOS_INFO, "T132 romstage: SDRAM init done by BootROM, RAMCODE = %d\n",
 		sdram_get_ram_code());
@@ -81,6 +90,8 @@ void romstage(void)
 	printk(BIOS_INFO, "T132 romstage: sdram_init done\n");
 #endif
 
+	timestamp_add_now(TS_AFTER_INITRAM);
+
 	/*
 	 * Trust Zone needs to be initialized after the DRAM initialization
 	 * because carveout registers are programmed during DRAM init.
@@ -114,6 +125,8 @@ void romstage(void)
 
 	cbmemc_reinit();
 
+	timestamp_add_now(TS_END_ROMSTAGE);
+
 	ccplex_cpu_start(entry);
 
 	clock_halt_avp();

src/soc/nvidia/tegra132/verstage.c

@@ -21,6 +21,7 @@
 #include <arch/exception.h>
 #include <console/console.h>
 #include <soc/verstage.h>
+#include <timestamp.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 void __attribute__((weak)) verstage_mainboard_init(void)
@@ -31,6 +32,7 @@ void __attribute__((weak)) verstage_mainboard_init(void)
 void main(void)
 {
 	console_init();
+	timestamp_add_now(TS_START_VBOOT);
 	exception_init();
 
 	verstage_mainboard_init();