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intel/sandybridge: Use postcar_frame for MTRR setup

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Adapt implementation from skylake.

Change-Id: Ica3134a2261d3e84c714264cf75557322f9ef5db
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17673
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-12-01 10:48:43 +02:00
commit b84c833bfd
2 changed files with 36 additions and 60 deletions
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24
src/cpu/intel/model_206ax/cache_as_ram.inc
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@ -225,12 +225,29 @@ before_romstage:
post_code(0x38)
/* Get number of MTRRs. */
/* Clear all of the variable MTRRs. */
popl %ebx
movl $MTRR_PHYS_BASE(0), %ecx
clr %eax
clr %edx
1:
testl %ebx, %ebx
jz 1f
wrmsr /* Write MTRR base. */
inc %ecx
wrmsr /* Write MTRR mask. */
inc %ecx
dec %ebx
jmp 1b
1:
/* Get number of MTRRs. */
popl %ebx
movl $MTRR_PHYS_BASE(0), %ecx
2:
testl %ebx, %ebx
jz 2f
/* Low 32 bits of MTRR base. */
popl %eax
@ -248,8 +265,9 @@ before_romstage:
inc %ecx
dec %ebx
jmp 1b
1:
jmp 2b
2:
post_code(0x39)
/* And enable cache again after setting MTRRs. */