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util/spd_tools/src/spd_gen/lp5.go: Support LP5X 9600Mbps

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Add support for LP5X 9600Mbps in SPD tool.

BUG=None
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: I1425fe08e3891f4a0a0627c8ab429ec72c06ffc5
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90867
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Ma, Zhixing <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit is contained in:
Bora Guvendik 2026-01-22 08:17:08 -08:00 • committed by Matt DeVillier
commit b6ebb24a48
1 changed files with 5 additions and 0 deletions
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5
util/spd_tools/src/spd_gen/lp5.go
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@ -209,6 +209,7 @@ var LP5SetInfo = map[int]LP5Set{
* = 1 / (speed grade / 2 / WCK:CK) // "double data rate"
*/
speedToTCKMinPs: map[int]int{
9600: 833, /* 1 / (9600 / 2 / 4) */
8533: 937, /* 1 / (8533 / 2 / 4) */
7500: 1066, /* 1 / (7500 / 2 / 4) */
6400: 1250, /* 1 / (6400 / 2 / 4) */
@ -374,6 +375,10 @@ var LP5BankArchToSPDEncoding = map[int]LP5BankArchParams{
* From Table 220 of JESD209-5B, using a 4:1 WCK:CK ratio and Set 0.
*/
var LP5SpeedMbpsToSPDEncoding = map[int]LP5SpeedParams{
9600: {
defaultTCKMinPs: 208, /* 1 / (9600 / 2) */
MaxCASLatency: 26,
},
8533: {
defaultTCKMinPs: 234, /* 1 / (8533 / 2) */
MaxCASLatency: 23,