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Improve the setup of MTRRs in stage1 to handle alignment and power of

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2 size calculations.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1133 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Marc Jones 2009-02-15 18:12:34 +00:00
commit b6c89edb04
3 changed files with 162 additions and 49 deletions
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8
include/arch/x86/mtrr.h
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@ -35,12 +35,10 @@
void x86_setup_var_mtrrs(unsigned address_bits);
void x86_setup_mtrrs(unsigned address_bits);
int x86_mtrr_check(void);
void stage1_set_var_mtrr(unsigned long reg, unsigned long base,
unsigned long size, unsigned long type);
void stage1_set_fix_mtrr(u32 reg, u8 type);
void stage1_set_var_mtrr_x(unsigned long reg, u32 base_lo, u32 base_hi,
u32 size_lo, u32 size_hi, unsigned long type);
u8 stage1_range_to_mtrr(u8 reg, u32 range_startk, u32 range_sizek,
u8 type, u32 address_bits);
u32 stage1_resk(u64 value);
#endif