From b63ae3a26537d845818483542db4dd6b0616bdc1 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Thu, 23 Feb 2017 22:06:01 -0700 Subject: [PATCH] UPSTREAM: mainboard/amd/gardenia: Remove PMxEE write on S4 resume Delete the write to PM register 0xee. This register is not listed in the current BKDG and S4 is not currently supported on this APU. NDA document #47517 "A55/.../A85X fusion Controller Hub Register Reference Guide" provides some clues on the intent of this write. This register has always been observed to power on with a value of 0x08 so the write has no effect. This should be revisited again when SMI and PSP fully implement the support required for S3. BUG=none BRANCH=none TEST=none Change-Id: I7c01148c21a07b51848f59e85161cb30450fa7a2 Signed-off-by: Patrick Georgi Original-Commit-Id: 7e438af99575365a97f87f59e83e1224571ac5c2 Original-Change-Id: I35e6c5f7ad1de7f51b018543d2f7ce82182f11e4 Original-Signed-off-by: Marc Jones Original-Reviewed-on: https://review.coreboot.org/18494 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/486780 --- src/mainboard/amd/gardenia/romstage.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c index 0136a98344..75674a090a 100644 --- a/src/mainboard/amd/gardenia/romstage.c +++ b/src/mainboard/amd/gardenia/romstage.c @@ -66,11 +66,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* TODO: Disable cache is not ok. */ disable_cache_as_ram(); - if (acpi_is_wakeup_s4()) { - outb(0xEE, PM_INDEX); - outb(0x8, PM_DATA); - } - post_code(0x50); copy_and_run();