From b4c6984a40714d0ab54d83dff24ab8cd9765fd46 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 12 May 2025 12:43:10 +0530
Subject: [PATCH] soc/qualcomm/x1p42100: Initialize QSPI and QUPv3 in bootblock

The bootblock requires early initialization of the Quad-SPI (QSPI)
controller to enable reading firmware from flash memory.

This commit adds calls to `quadspi_init()` with a 50 MHz bus clock
and `qupv3_fw_init()` within `bootblock_soc_init()`. This ensures
that the essential hardware for flash access and related QUPv3
functions are properly configured during the boot process.

BUG=b:404985109
TEST=Able to build google/bluey.

Change-Id: Ia32114527f4b7cbabef1c1f8b7ad6d2d4b71c1f8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: mukesh.savaliya
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/bootblock.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/soc/qualcomm/x1p42100/bootblock.c b/src/soc/qualcomm/x1p42100/bootblock.c
index a4cedfa69f..32a958b687 100644
--- a/src/soc/qualcomm/x1p42100/bootblock.c
+++ b/src/soc/qualcomm/x1p42100/bootblock.c
@@ -2,9 +2,16 @@
 
 #include <bootblock_common.h>
 #include <soc/mmu.h>
+#include <soc/qspi_common.h>
+#include <soc/qupv3_config_common.h>
+
+#define SPI_BUS_CLOCK_FREQ (50 * MHz)
 
 void bootblock_soc_init(void)
 {
 	if (!CONFIG(COMPRESS_BOOTBLOCK))
 		soc_mmu_init();
+
+	quadspi_init(SPI_BUS_CLOCK_FREQ);
+	qupv3_fw_init();
 }