diff --git a/src/mainboard/google/rauru/Makefile.mk b/src/mainboard/google/rauru/Makefile.mk
index d383629b5a..98f5bbd8c3 100644
--- a/src/mainboard/google/rauru/Makefile.mk
+++ b/src/mainboard/google/rauru/Makefile.mk
@@ -8,5 +8,6 @@ bootblock-y += bootblock.c
 
 romstage-y += romstage.c
 
+ramstage-y += boardid.c
 ramstage-y += mainboard.c
 ramstage-y += regulator.c
diff --git a/src/mainboard/google/rauru/boardid.c b/src/mainboard/google/rauru/boardid.c
new file mode 100644
index 0000000000..1d49e03b6a
--- /dev/null
+++ b/src/mainboard/google/rauru/boardid.c
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <assert.h>
+#include <boardid.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include <soc/mt6363_sdmadc.h>
+
+#include "storage.h"
+
+#define ADC_LEVELS 8
+
+enum {
+	/* Storage IDs */
+	STORAGE_ID_LOW_CHANNEL = AUXADC_CHAN_VIN1,
+};
+
+static const unsigned int storageid_voltages[ADC_LEVELS] = {
+	/* ID : Voltage (unit: mV) */
+	[0]  =   50,
+	[1]  =  210,
+	[2]  =  420,
+	[3]  =  620,
+	[4]  =  820,
+	[5]  = 1040,
+	[6]  = 1240,
+	[7]  = 1450,
+};
+
+static const unsigned int *adc_voltages[] = {
+	[STORAGE_ID_LOW_CHANNEL] = storageid_voltages,
+};
+
+static uint32_t get_adc_index(unsigned int channel)
+{
+	int value;
+
+	mt6363_sdmadc_read(channel, &value, SDMADC_OPEN, AUXADC_VAL_PROCESSED);
+	assert(channel < ARRAY_SIZE(adc_voltages));
+	const unsigned int *voltages = adc_voltages[channel];
+	assert(voltages);
+
+	/* Find the closest voltage */
+	uint32_t id;
+	for (id = 0; id < ADC_LEVELS - 1; id++)
+		if (value < (voltages[id] + voltages[id + 1]) / 2)
+			break;
+
+	printk(BIOS_DEBUG, "ADC[%u]: Raw value=%u ID=%u\n", channel, value, id);
+	return id;
+}
+
+uint32_t storage_id(void)
+{
+	static uint32_t cached_storage_id = BOARD_ID_INIT;
+
+	if (cached_storage_id == BOARD_ID_INIT)
+		cached_storage_id = get_adc_index(STORAGE_ID_LOW_CHANNEL);
+
+	printk(BIOS_DEBUG, "Storage ID: %#02x\n", cached_storage_id);
+	return cached_storage_id;
+}
+
+enum ufs_type storage_type(uint32_t index)
+{
+	switch (index) {
+	case 0:
+		return UFS_40;
+	case 1:
+		return UFS_31;
+	case 2:
+		return UFS_40_HS;
+	default:
+		printk(BIOS_DEBUG, "unsupported type %d\n", index);
+	}
+	return UFS_UNKNOWN;
+}
diff --git a/src/mainboard/google/rauru/romstage.c b/src/mainboard/google/rauru/romstage.c
index b6f0d4eb17..6ecaf61af4 100644
--- a/src/mainboard/google/rauru/romstage.c
+++ b/src/mainboard/google/rauru/romstage.c
@@ -3,6 +3,7 @@
 #include <arch/stages.h>
 #include <soc/emi.h>
 #include <soc/irq2axi.h>
+#include <soc/mt6363.h>
 #include <soc/mtk_pwrsel.h>
 #include <soc/pcie.h>
 
@@ -10,6 +11,9 @@ void platform_romstage_main(void)
 {
 	irq2axi_disable();
 	pwrsel_init();
+	mt6363_init_pmif_arb();
+	mt6363_enable_vtref18(true);
+	mt6363_set_vtref18_voltage(1800000);
 	mtk_dram_init();
 
 	if (CONFIG(PCI))
diff --git a/src/mainboard/google/rauru/storage.h b/src/mainboard/google/rauru/storage.h
new file mode 100644
index 0000000000..a97bbcbb58
--- /dev/null
+++ b/src/mainboard/google/rauru/storage.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __MAINBOARD_GOOGLE_RAURU_STORAGE_H__
+#define __MAINBOARD_GOOGLE_RAURU_STORAGE_H__
+
+enum ufs_type {
+	UFS_UNKNOWN = 0,
+	UFS_31 = 0x310,
+	UFS_40 = 0x400,
+	UFS_40_HS = 0x401,
+};
+
+uint32_t storage_id(void);
+enum ufs_type storage_type(uint32_t index);
+
+#endif