From b38a6eec1ce8fcf6f765b64f3ee870e3a2730848 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Mon, 18 Dec 2000 03:21:04 +0000 Subject: [PATCH] More chipset setup for ram. --- src/northbridge/acer/m1631/chipset_init.inc | 2 ++ src/northbridge/acer/m1631/raminit.inc | 20 ++++++++++++++++++-- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/src/northbridge/acer/m1631/chipset_init.inc b/src/northbridge/acer/m1631/chipset_init.inc index 989b240824..4f4048ff18 100644 --- a/src/northbridge/acer/m1631/chipset_init.inc +++ b/src/northbridge/acer/m1631/chipset_init.inc @@ -1,5 +1,7 @@ /* SPD ram init */ #define PM_DEVFN CONFIG_ADDR(0, 0, 0) +.type chipsetinit_start, @function + jmpl chipsetinit_start /* table of settings for initial registers */ /* format is register #, and value, OR value */ diff --git a/src/northbridge/acer/m1631/raminit.inc b/src/northbridge/acer/m1631/raminit.inc index 81f1b29453..b0bfff53fa 100644 --- a/src/northbridge/acer/m1631/raminit.inc +++ b/src/northbridge/acer/m1631/raminit.inc @@ -1,4 +1,5 @@ -#if 0 +.type raminit_start, @function + /*** *** sungeun *** @@ -224,7 +225,7 @@ internal_bank_tbl: *** END MACROS ***/ - +#if 0 /*** *** START REAL STUFF ***/ @@ -809,6 +810,21 @@ configure_next: #define INIT_MCR $0xf6621000 #define WRITE_MCR0 movl %ecx, %eax ; outl %eax, %dx /*#include */ +raminit_start: + mov $0x81,%ax + mov $0x7f00,%cx /*** disable SMA mode ***/ + pci_read_write_byte + mov $0x82,%ax + mov $0xff10,%cx /*** set 3 DIMMs, no ECC ***/ + pci_read_write_byte + mov $0x84,%ax + mov $0xfe00,%cx /*** set 3 DIMMs, no ECC ***/ + pci_read_write_byte + + /*** initialize, load table, zero %ecx, %ebx ***/ + movl $mem_bank_reg_table,%esi + xor %ecx,%ecx + xor %ebx,%ebx /* make the flash writeable */ /* select the south bridge, register 44 (base) */