From b31e62ae5cc8bdc4b10103e7d39cd30d07bc0185 Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Thu, 20 Nov 2025 12:21:13 -0800 Subject: [PATCH] mb/intel/ptlrvp: Add LPCAMM T3 RVP board support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for Pantherlake LPCAMM T3 Reference Validation Platform: - Define PTLP_LPCAMM_T3_RVP board ID (0x02) - Add memory configuration for LPCAMM including DQ/DQS mapping - Configure SPD information for LPCAMM modules using SMBus address 0x50 across all channels with MEM_TOPO_LP5_CAMM topology to enable SPD detection BUG=none TEST=Boot LPCAMM T3 RVP and verify memory detection. Change-Id: I17325241c105a5af5a97931be5c75a025b2bd7c8 Signed-off-by: Bora Guvendik Reviewed-on: https://review.coreboot.org/c/coreboot/+/90139 Reviewed-by: Kim, Wonkyu Reviewed-by: Jérémy Compostella Tested-by: build bot (Jenkins) --- .../baseboard/include/baseboard/variants.h | 1 + .../intel/ptlrvp/variants/ptlrvp/gpio.c | 1 + .../intel/ptlrvp/variants/ptlrvp/memory.c | 79 +++++++++++++++++++ 3 files changed, 81 insertions(+) diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h index 05ddf5bb5f..9378a33e84 100644 --- a/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h @@ -12,6 +12,7 @@ enum ptl_boardid { PTLP_LP5_T3_RVP = 0x01, + PTLP_LPCAMM_T3_RVP = 0x02, PTLP_LP5_T4_RVP = 0x03, PTLP_DDR5_RVP = 0x04, GCS_32GB = 0x11, diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c index c2913c48d3..9d32ff3431 100644 --- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c +++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c @@ -455,6 +455,7 @@ const struct pad_config *variant_board_gpio_diff_table(size_t *num) switch (board_id) { case PTLP_LP5_T3_RVP: + case PTLP_LPCAMM_T3_RVP: return NULL; case PTLP_LP5_T4_RVP: *num = ARRAY_SIZE(t4_gpio_diff_table); diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c index 4882edb324..de17b261a9 100644 --- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c +++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c @@ -121,6 +121,64 @@ static const struct mb_cfg lp5_t3_mem_config = { }, }; +static const struct mb_cfg camm_t3_mem_config = { + .type = MEM_TYPE_LP5X, + + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 0, 3, 1, 2, 6, 7, 4, 5, }, + .dq1 = { 13, 12, 15, 14, 8, 10, 11, 9 }, + }, + .ddr1 = { + .dq0 = { 8, 10, 11, 9, 13, 15, 14, 12, }, + .dq1 = { 5, 7, 6, 4, 3, 2, 1, 0 }, + }, + .ddr2 = { + .dq0 = { 1, 3, 0, 2, 6, 7, 5, 4 }, + .dq1 = { 12, 13, 15, 14, 8, 11, 9, 10, }, + }, + .ddr3 = { + .dq0 = { 14, 15, 12, 13, 10, 8, 11, 9, }, + .dq1 = { 4, 6, 7, 5, 1, 3, 0, 2 }, + }, + .ddr4 = { + .dq0 = { 3, 0, 2, 1, 6, 7, 4, 5 }, + .dq1 = { 13, 12, 15, 14, 8, 10, 11, 9, }, + }, + .ddr5 = { + .dq0 = { 10, 8, 11, 9, 13, 15, 12, 14, }, + .dq1 = { 2, 1, 3, 0, 7, 6, 5, 4 }, + }, + .ddr6 = { + .dq0 = { 3, 1, 2, 0, 5, 7, 4, 6, }, + .dq1 = { 12, 14, 15, 13, 9, 10, 11, 8 }, + }, + .ddr7 = { + .dq0 = { 8, 9, 10, 11, 12, 13, 14, 15, }, + .dq1 = { 5, 6, 7, 4, 2, 1, 3, 0 }, + }, + }, + + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr5 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 1, .dqs1 = 0 } + }, + + .ect = true, /* Early Command Training */ + + .user_bd = BOARD_TYPE_ULT_ULX, + + .lp5x_config = { + .ccc_config = 0x55, + }, +}; + static const struct mb_cfg lp5_t4_mem_config = { .type = MEM_TYPE_LP5X, @@ -200,6 +258,8 @@ const struct mb_cfg *variant_memory_params(void) int board_id = get_rvp_board_id(); switch (board_id) { + case PTLP_LPCAMM_T3_RVP: + return &camm_t3_mem_config; case PTLP_LP5_T3_RVP: return &lp5_t3_mem_config; case PTLP_LP5_T4_RVP: @@ -220,6 +280,25 @@ void variant_get_spd_info(struct mem_spd *spd_info) int board_id = get_rvp_board_id(); switch (board_id) { + case PTLP_LPCAMM_T3_RVP: + spd_info->topo = MEM_TOPO_LP5_CAMM; + spd_info->smbus[0].addr_dimm[0] = 0x50; + spd_info->smbus[0].addr_dimm[1] = 0x0; + spd_info->smbus[1].addr_dimm[0] = 0x50; + spd_info->smbus[1].addr_dimm[1] = 0x0; + spd_info->smbus[2].addr_dimm[0] = 0x50; + spd_info->smbus[2].addr_dimm[1] = 0x0; + spd_info->smbus[3].addr_dimm[0] = 0x50; + spd_info->smbus[3].addr_dimm[1] = 0x0; + spd_info->smbus[4].addr_dimm[0] = 0x50; + spd_info->smbus[4].addr_dimm[1] = 0x0; + spd_info->smbus[5].addr_dimm[0] = 0x50; + spd_info->smbus[5].addr_dimm[1] = 0x0; + spd_info->smbus[6].addr_dimm[0] = 0x50; + spd_info->smbus[6].addr_dimm[1] = 0x0; + spd_info->smbus[7].addr_dimm[0] = 0x50; + spd_info->smbus[7].addr_dimm[1] = 0x0; + break; case PTLP_LP5_T3_RVP: case PTLP_LP5_T4_RVP: case GCS_32GB: