From b2b1eb3c5a252dd5831a5fa39b45e771c810c88e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Mon, 6 Oct 2025 14:16:36 +0200
Subject: [PATCH] soc/amd/common/block/smn: Add simple SMN I/O accessors
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Add PCI I/O-based SMN accessors. These accessors can be used for
early workarounds when the PCI ECAM MMCONF is not working yet.
An example of such workaround is the patching of PCI ECAM MMCONF
base address in Turin SoC, which has to be done via SMN, but it
cannot use PCI ECAM MMCONF to access SMN yet.

Change-Id: I5e0faaa48e4d7b4479e3af9b795ad2a879f569fd
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 .../amd/common/block/include/amdblocks/smn.h  |  8 +++++++
 src/soc/amd/common/block/smn/smn.c            | 22 +++++++++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/src/soc/amd/common/block/include/amdblocks/smn.h b/src/soc/amd/common/block/include/amdblocks/smn.h
index 0268926bbe..ad6972114e 100644
--- a/src/soc/amd/common/block/include/amdblocks/smn.h
+++ b/src/soc/amd/common/block/include/amdblocks/smn.h
@@ -9,4 +9,12 @@ uint32_t smn_read32(uint32_t reg);
 uint64_t smn_read64(uint32_t reg);
 void smn_write32(uint32_t reg, uint32_t val);
 
+#if defined(__SIMPLE_DEVICE__)
+
+uint32_t smn_io_read32(uint32_t reg);
+uint64_t smn_io_read64(uint32_t reg);
+void smn_io_write32(uint32_t reg, uint32_t val);
+
+#endif
+
 #endif /* AMD_BLOCK_SMN_H */
diff --git a/src/soc/amd/common/block/smn/smn.c b/src/soc/amd/common/block/smn/smn.c
index caf6a41004..41396701e2 100644
--- a/src/soc/amd/common/block/smn/smn.c
+++ b/src/soc/amd/common/block/smn/smn.c
@@ -25,3 +25,25 @@ void smn_write32(uint32_t reg, uint32_t val)
 	pci_write_config32(SOC_GNB_DEV, SMN_INDEX_ADDR, reg);
 	pci_write_config32(SOC_GNB_DEV, SMN_DATA_ADDR, val);
 }
+
+
+#if defined(__SIMPLE_DEVICE__)
+
+uint32_t smn_io_read32(uint32_t reg)
+{
+	pci_io_write_config32(SOC_GNB_DEV, SMN_INDEX_ADDR, reg);
+	return pci_io_read_config32(SOC_GNB_DEV, SMN_DATA_ADDR);
+}
+
+uint64_t smn_io_read64(uint32_t reg)
+{
+	return smn_io_read32(reg) | (uint64_t)smn_io_read32(reg + 4) << 32;
+}
+
+void smn_io_write32(uint32_t reg, uint32_t val)
+{
+	pci_io_write_config32(SOC_GNB_DEV, SMN_INDEX_ADDR, reg);
+	pci_io_write_config32(SOC_GNB_DEV, SMN_DATA_ADDR, val);
+}
+
+#endif