diff --git a/src/mainboard/google/hatch/variants/duffy/overridetree.cb b/src/mainboard/google/hatch/variants/duffy/overridetree.cb
index 2f36bc8b62..ade12c5806 100644
--- a/src/mainboard/google/hatch/variants/duffy/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/duffy/overridetree.cb
@@ -22,7 +22,14 @@ chip soc/intel/cannonlake
 
 	# USB configuration
 	register "usb2_ports[0]" = "USB2_PORT_MID(OC2)"        # Type-A Port 2
-	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
+	register "usb2_ports[1]" = "{
+		.enable = 1,
+		.ocpin = OC1,
+		.tx_bias = USB2_BIAS_0MV,
+		.tx_emp_enable = USB2_PRE_EMP_ON,
+		.pre_emp_bias  = USB2_BIAS_28P15MV,
+		.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP,
+	}" # Type-A Port 1
 	register "usb2_ports[2]" = "{
 		.enable = 1,
 		.ocpin = OC3,
@@ -31,14 +38,7 @@ chip soc/intel/cannonlake
 		.pre_emp_bias  = USB2_BIAS_28P15MV,
 		.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP,
 	}" # Type-A Port 3
-	register "usb2_ports[3]" = "{
-		.enable = 1,
-		.ocpin = OC1,
-		.tx_bias = USB2_BIAS_0MV,
-		.tx_emp_enable = USB2_PRE_EMP_ON,
-		.pre_emp_bias  = USB2_BIAS_28P15MV,
-		.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP,
-	}" # Type-A Port 1
+	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
 	register "usb2_ports[4]" = "{
 		.enable = 1,
 		.ocpin = OC_SKIP,
diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
index db05302278..e2380f4460 100644
--- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
@@ -22,7 +22,14 @@ chip soc/intel/cannonlake
 
 	# USB configuration
 	register "usb2_ports[0]" = "USB2_PORT_MID(OC2)"        # Type-A Port 2
-	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
+	register "usb2_ports[1]" = "{
+		.enable = 1,
+		.ocpin = OC1,
+		.tx_bias = USB2_BIAS_0MV,
+		.tx_emp_enable = USB2_PRE_EMP_ON,
+		.pre_emp_bias  = USB2_BIAS_28P15MV,
+		.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP,
+	}" # Type-A Port 1
 	register "usb2_ports[2]" = "{
 		.enable = 1,
 		.ocpin = OC3,
@@ -31,14 +38,7 @@ chip soc/intel/cannonlake
 		.pre_emp_bias  = USB2_BIAS_28P15MV,
 		.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP,
 	}" # Type-A Port 3
-	register "usb2_ports[3]" = "{
-		.enable = 1,
-		.ocpin = OC1,
-		.tx_bias = USB2_BIAS_0MV,
-		.tx_emp_enable = USB2_PRE_EMP_ON,
-		.pre_emp_bias  = USB2_BIAS_28P15MV,
-		.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP,
-	}" # Type-A Port 1
+	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
 	register "usb2_ports[4]" = "{
 		.enable = 1,
 		.ocpin = OC_SKIP,