diff --git a/src/vendorcode/amd/fsp/cezanne/soc_dmi_info.h b/src/vendorcode/amd/fsp/cezanne/soc_dmi_info.h
index bbc67bf5fa..76f165d061 100644
--- a/src/vendorcode/amd/fsp/cezanne/soc_dmi_info.h
+++ b/src/vendorcode/amd/fsp/cezanne/soc_dmi_info.h
@@ -10,6 +10,7 @@
 #define AGESA_STRUCT_SOCKET_COUNT         2   ///< Number of sockets in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_CHANNELS_PER_SOCKET  8   ///< Channels per socket in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_DIMMS_PER_CHANNEL    4   ///< DIMMs per channel in AGESA FSP DMI T17 table
+#define AGESA_STRUCT_PART_NUMBER_SIZE     21
 
 #define SMBIOS_3_2_3_3_SUPPORT            1
 
diff --git a/src/vendorcode/amd/fsp/common/dmi_info.h b/src/vendorcode/amd/fsp/common/dmi_info.h
index 390732df6f..5593d760f5 100644
--- a/src/vendorcode/amd/fsp/common/dmi_info.h
+++ b/src/vendorcode/amd/fsp/common/dmi_info.h
@@ -157,7 +157,7 @@ typedef struct {
   OUT UINT16                    Speed;                  ///< Identifies the speed of the device, in megahertz (MHz).
   OUT UINT64                    ManufacturerIdCode;     ///< Manufacturer ID code.
   OUT CHAR8                     SerialNumber[9];        ///< Serial Number.
-  OUT CHAR8                     PartNumber[21];         ///< Part Number.
+  OUT CHAR8                     PartNumber[AGESA_STRUCT_PART_NUMBER_SIZE]; ///< Part Number.
   OUT UINT8                     Attributes;             ///< Bits 7-4: Reserved, Bits 3-0: rank.
   OUT UINT32                    ExtSize;                ///< Extended Size.
   OUT UINT16                    ConfigSpeed;            ///< Configured memory clock speed
diff --git a/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h b/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h
index 08f5f5cd1b..9ff71b124d 100644
--- a/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h
+++ b/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h
@@ -11,6 +11,7 @@
 #define AGESA_STRUCT_SOCKET_COUNT         2   ///< Number of sockets in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_CHANNELS_PER_SOCKET  8   ///< Channels per socket in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_DIMMS_PER_CHANNEL    4   ///< DIMMs per channel in AGESA FSP DMI T17 table
+#define AGESA_STRUCT_PART_NUMBER_SIZE     31
 
 #define SMBIOS_3_2_3_3_SUPPORT            1
 
diff --git a/src/vendorcode/amd/fsp/mendocino/soc_dmi_info.h b/src/vendorcode/amd/fsp/mendocino/soc_dmi_info.h
index 12f3e8fa57..1c3cb1a0b1 100644
--- a/src/vendorcode/amd/fsp/mendocino/soc_dmi_info.h
+++ b/src/vendorcode/amd/fsp/mendocino/soc_dmi_info.h
@@ -10,6 +10,7 @@
 #define AGESA_STRUCT_SOCKET_COUNT         4   ///< Number of sockets in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_CHANNELS_PER_SOCKET  12  ///< Channels per socket in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_DIMMS_PER_CHANNEL    2   ///< DIMMs per channel in AGESA FSP DMI T17 table
+#define AGESA_STRUCT_PART_NUMBER_SIZE     21
 
 #define SMBIOS_3_2_3_3_SUPPORT            1
 
diff --git a/src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h b/src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h
index 12f3e8fa57..1c3cb1a0b1 100644
--- a/src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h
+++ b/src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h
@@ -10,6 +10,7 @@
 #define AGESA_STRUCT_SOCKET_COUNT         4   ///< Number of sockets in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_CHANNELS_PER_SOCKET  12  ///< Channels per socket in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_DIMMS_PER_CHANNEL    2   ///< DIMMs per channel in AGESA FSP DMI T17 table
+#define AGESA_STRUCT_PART_NUMBER_SIZE     21
 
 #define SMBIOS_3_2_3_3_SUPPORT            1
 
diff --git a/src/vendorcode/amd/fsp/picasso/soc_dmi_info.h b/src/vendorcode/amd/fsp/picasso/soc_dmi_info.h
index 109a01a6e0..94a43f55b0 100644
--- a/src/vendorcode/amd/fsp/picasso/soc_dmi_info.h
+++ b/src/vendorcode/amd/fsp/picasso/soc_dmi_info.h
@@ -10,5 +10,6 @@
 #define AGESA_STRUCT_SOCKET_COUNT         1   ///< Number of sockets in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_CHANNELS_PER_SOCKET  4   ///< Channels per socket in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_DIMMS_PER_CHANNEL    4   ///< DIMMs per channel in AGESA FSP DMI T17 table
+#define AGESA_STRUCT_PART_NUMBER_SIZE     21
 
 #endif /* SOC_DMI_INFO_H */