From b1b8b0e8e1d5a9f09401283d0a59d0d68c8e3c6c Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Fri, 4 Apr 2025 13:05:13 +0100 Subject: [PATCH] mb/starlabs/starbook/tgl: Reconfigure PCH Strap GPIOs Configure all strap GPIOs as outputs, rather than some being not connected. This doesn't change anything, but is more explicit. Set these all to sample on RSMRST. Change-Id: I557bfc1339bad169753640c9404813305a16024e Signed-off-by: Sean Rhodes Reviewed-on: https://review.coreboot.org/c/coreboot/+/87172 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- src/mainboard/starlabs/starbook/variants/tgl/gpio.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c index 0aa6cbe7b4..82d1a21a0e 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c @@ -97,15 +97,17 @@ const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_B14, 0, RSMRST), /* Top Swap [ Disabled / Enabled ] */ PAD_CFG_GPO(GPP_B18, 0, RSMRST), /* Reboot Support [ Enabled / Disabled ] */ PAD_CFG_GPO(GPP_C2, 1, RSMRST), /* TLS Confidentiality [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_B23, 0, DEEP), /* XTAL [ 38.4Mhz / 19.2MHz ] */ - PAD_CFG_GPO(GPP_C5, 0, RSMRST), /* eSPI [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_B22, 0, RSMRST), /* eSPI [ Enabled / Disabled ] */ PAD_CFG_GPO(GPP_E6, 0, RSMRST), /* JTAG ODT [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_E21, 0, RSMRST), /* TBT LSX #1 [ 1.8V / 3.3V ] */ + PAD_CFG_GPO(GPP_C5, 0, RSMRST), /* BFX Strap 2 Bit 1 [ Disabled / Enabled ] */ PAD_CFG_GPO(GPP_H0, 0, RSMRST), /* BFX Strap 2 Bit 2 [ Disabled / Enabled ] */ PAD_CFG_GPO(GPP_H1, 0, RSMRST), /* BFX Strap 2 Bit 3 [ Disabled / Enabled ] */ PAD_CFG_GPO(GPP_H2, 0, RSMRST), /* BFX Strap 2 Bit 4 [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_E21, 0, RSMRST), /* TBT LSX #1 [ 1,8V / 3.3V ] */ PAD_CFG_GPO(GPP_F7, 0, RSMRST), /* MCRO LDO [ Disabled / Bypass ] */ PAD_CFG_GPO(GPD7, 0, RSMRST), /* RTC Clock Delay [ Disabled / 95ms ] */ + PAD_CFG_GPO(GPP_B23, 0, DEEP), /* CPUNSSC [ 19.2MHz / 38.4MHz ] */ + PAD_CFG_GPO(GPP_F10, 0, DEEP), /* XTAL Mode [ Attached / Single ] */ PAD_NC(GPD2, NONE), PAD_NC(GPD6, NONE), @@ -140,8 +142,6 @@ const struct pad_config gpio_table[] = { PAD_NC(GPP_B19, NONE), PAD_NC(GPP_B20, NONE), PAD_NC(GPP_B21, NONE), - PAD_NC(GPP_B22, NONE), - PAD_NC(GPP_C3, NONE), PAD_NC(GPP_C4, NONE), PAD_NC(GPP_C9, NONE), @@ -198,7 +198,6 @@ const struct pad_config gpio_table[] = { PAD_NC(GPP_F6, NONE), PAD_NC(GPP_F8, NONE), PAD_NC(GPP_F9, NONE), - PAD_NC(GPP_F10, NONE), PAD_NC(GPP_F11, NONE), PAD_NC(GPP_F12, NONE), PAD_NC(GPP_F13, NONE), @@ -213,6 +212,7 @@ const struct pad_config gpio_table[] = { PAD_NC(GPP_F22, NONE), PAD_NC(GPP_F23, NONE), + /* H3: Not Connected */ PAD_NC(GPP_H3, NONE), PAD_NC(GPP_H4, NONE), PAD_NC(GPP_H5, NONE),