soc/qualcomm/x1p42100: Add Clock support for USB Type-C ports
Enable clocks for Type-C ports C0 and C1. The register details are part of HRD-X1P42100-S1 document. https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/ BUG=b:448107633 TEST = Verified that all the clocks added are ON during usb init. BIT31[CLK OFF] of CBCR register of respective clock indicates clock status. Clock Configuration Status: Clock Name State Register Value ---------------------------------------------------------------- gcc_usb30_mp_master_clk ON 0x00117018 0x00000001 gcc_usb30_mp_sleep_clk ON 0x00117024 0x00000001 gcc_usb30_mp_mock_utmi_clk ON 0x00117028 0x00000001 gcc_usb3_mp_phy_aux_clk ON 0x00117288 0x00000001 gcc_usb3_mp_phy_com_aux_clk ON 0x0011728C 0x00000001 gcc_usb3_mp_phy_pipe_0_clk ON 0x00117290 0x00000001 gcc_usb3_mp_phy_pipe_1_clk ON 0x00117298 0x00000001 gcc_cfg_noc_usb3_mp_axi_clk ON 0x001173CC 0x00000001 gcc_aggre_usb3_mp_axi_clk ON 0x001173D0 0x00000001 gcc_sys_noc_usb_axi_clk ON 0x0012D014 0x00000001 gcc_cfg_noc_usb_anoc_north_ahb_clk ON 0x0012D028 0x00000000 gcc_cfg_noc_usb_anoc_south_ahb_clk ON 0x0012D02C 0x00000000 gcc_aggre_usb_noc_axi_clk ON 0x0012D034 0x00000001 gcc_cfg_noc_usb_anoc_ahb_clk ON 0x0012D024 0x00000000 gcc_usb30_prim_master_clk ON 0x00139018 0x00000001 gcc_usb30_prim_sleep_clk ON 0x00139024 0x00000001 gcc_usb30_prim_mock_utmi_clk ON 0x00139028 0x00000001 gcc_usb3_prim_phy_com_aux_clk ON 0x00139064 0x00000001 gcc_usb3_prim_phy_pipe_clk ON 0x00139068 0x00000001 gcc_cfg_noc_usb3_prim_axi_clk ON 0x0013908C 0x00000001 gcc_aggre_usb3_prim_axi_clk ON 0x00139090 0x00000001 gcc_cfg_noc_usb3_sec_axi_clk ON 0x001A108C 0x00000001 gcc_aggre_usb3_sec_axi_clk ON 0x001A1090 0x00000001 gcc_usb30_sec_master_clk ON 0x001A1018 0x00000001 gcc_usb30_sec_sleep_clk ON 0x001A1024 0x00000001 gcc_usb30_sec_mock_utmi_clk ON 0x001A1028 0x00000001 gcc_usb3_sec_phy_aux_clk ON 0x001A1060 0x00000001 gcc_usb3_sec_phy_com_aux_clk ON 0x001A1064 0x00000001 gcc_usb3_sec_phy_pipe_clk ON 0x001A1068 0x00000001 Change-Id: I86cd84f515a22a080fe39687c8b7b8c01cb9c001 Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89350 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Hari L
Subrata Banik
parent
c7e4ef822d
commit
b18dfde22a
3 changed files with 274 additions and 33 deletions
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@ -239,9 +239,11 @@ static u32 *usb_gdsc[MAX_USB_GDSC] = {
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[USB30_MP_GDSC] = &gcc->gcc_usb30_mp_gdscr,
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[USB3_SS0_PHY_GDSC] = &gcc->gcc_usb3_mp_ss0_phy_gdscr,
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[USB3_SS1_PHY_GDSC] = &gcc->gcc_usb3_mp_ss1_phy_gdscr,
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[USB30_PRIM_GDSC] = &gcc->gcc_usb30_prim_gdscr,
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[USB30_SEC_GDSC] = &gcc->gcc_usb30_sec_gdscr,
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};
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static u32 *usb_cbcr[USB_CLK_COUNT] = {
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static u32 *usb_mp_cbcr[USB_CLK_COUNT] = {
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[USB30_MP_MASTER_CBCR] = &gcc->gcc_usb30_mp_master_cbcr,
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[USB30_MP_SLEEP_CBCR] = &gcc->gcc_usb30_mp_sleep_cbcr,
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[USB30_MP_MOCK_UTMI_CBCR] = &gcc->gcc_usb30_mp_mock_utmi_cbcr,
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@ -259,6 +261,39 @@ static u32 *usb_cbcr[USB_CLK_COUNT] = {
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[AGGRE_NOC_USB_NORTH_AXI_CBCR] = &gcc->gcc_aggre_noc_usb_north_axi_cbcr,
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};
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static u32 *usb_prim_cbcr[USB_PRIM_CLK_COUNT] = {
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[USB_PRIM_SYS_NOC_USB_AXI_CBCR] = &gcc->gcc_sys_noc_usb_axi_cbcr,
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[USB_PRIM_CFG_NOC_USB_ANOC_AHB_CBCR] = &gcc->gcc_cfg_noc_usb_anoc_ahb_cbcr,
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[USB_PRIM_CFG_NOC_USB_ANOC_NORTH_AHB_CBCR] = &gcc->gcc_cfg_noc_usb_anoc_north_ahb_cbcr,
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[USB_PRIM_CFG_NOC_USB_ANOC_SOUTH_AHB_CBCR] = &gcc->gcc_cfg_noc_usb_anoc_south_ahb_cbcr,
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[USB_PRIM_AGGRE_USB_NOC_AXI_CBCR] = &gcc->gcc_aggre_usb_noc_axi_cbcr,
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[USB_PRIM_AGGRE_NOC_USB_SOUTH_AXI_CBCR] = &gcc->gcc_aggre_noc_usb_south_axi_cbcr,
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[USB_PRIM_AGGRE_NOC_USB_NORTH_AXI_CBCR] = &gcc->gcc_aggre_noc_usb_north_axi_cbcr,
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[USB_PRIM_USB30_PRIM_MASTER_CBCR] = &gcc->gcc_usb30_prim_master_cbcr,
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[USB_PRIM_USB30_PRIM_SLEEP_CBCR] = &gcc->gcc_usb30_prim_sleep_cbcr,
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[USB_PRIM_USB30_PRIM_MOCK_UTMI_CBCR] = &gcc->gcc_usb30_prim_mock_utmi_cbcr,
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[USB_PRIM_USB3_PRIM_PHY_AUX_CBCR] = &gcc->gcc_usb3_prim_phy_aux_cbcr,
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[USB_PRIM_USB3_PRIM_PHY_COM_AUX_CBCR] = &gcc->gcc_usb3_prim_phy_com_aux_cbcr,
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[USB_PRIM_USB3_PRIM_PHY_PIPE_CBCR] = &gcc->gcc_usb3_prim_phy_pipe_cbcr,
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[USB_PRIM_CFG_NOC_USB3_PRIM_AXI_CBCR] = &gcc->gcc_cfg_noc_usb3_prim_axi_cbcr,
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[USB_PRIM_AGGRE_USB3_PRIM_AXI_CBCR] = &gcc->gcc_aggre_usb3_prim_axi_cbcr,
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};
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static u32 *usb_sec_cbcr[USB_SEC_CLK_COUNT] = {
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[USB_SEC_CFG_NOC_USB3_SEC_AXI_CBCR] = &gcc->gcc_cfg_noc_usb3_sec_axi_cbcr,
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[USB_SEC_AGGRE_USB3_SEC_AXI_CBCR] = &gcc->gcc_aggre_usb3_sec_axi_cbcr,
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[USB_SEC_USB30_SEC_MASTER_CBCR] = &gcc->gcc_usb30_sec_master_cbcr,
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[USB_SEC_USB30_SEC_SLEEP_CBCR] = &gcc->gcc_usb30_sec_sleep_cbcr,
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[USB_SEC_USB30_SEC_MOCK_UTMI_CBCR] = &gcc->gcc_usb30_sec_mock_utmi_cbcr,
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[USB_SEC_USB3_SEC_PHY_AUX_CBCR] = &gcc->gcc_usb3_sec_phy_aux_cbcr,
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[USB_SEC_USB3_SEC_PHY_COM_AUX_CBCR] = &gcc->gcc_usb3_sec_phy_com_aux_cbcr,
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[USB_SEC_USB3_SEC_PHY_PIPE_CBCR] = &gcc->gcc_usb3_sec_phy_pipe_cbcr,
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[USB_SEC_AGGRE_USB_NOC_AXI_CBCR] = &gcc->gcc_aggre_usb_noc_axi_cbcr,
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[USB_SEC_AGGRE_NOC_USB_NORTH_AXI_CBCR] = &gcc->gcc_aggre_noc_usb_north_axi_cbcr,
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[USB_SEC_AGGRE_NOC_USB_SOUTH_AXI_CBCR] = &gcc->gcc_aggre_noc_usb_south_axi_cbcr,
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[USB_SEC_SYS_NOC_USB_AXI_CBCR] = &gcc->gcc_sys_noc_usb_axi_cbcr,
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};
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static struct clock_freq_config pcie_core_cfg[] = {
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{
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.hz = 100 * MHz,
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@ -385,18 +420,54 @@ enum cb_err usb_clock_enable(enum clk_usb clk_type)
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if (clk_type >= USB_CLK_COUNT)
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return CB_ERR;
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return clock_enable(usb_cbcr[clk_type]);
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return clock_enable(usb_mp_cbcr[clk_type]);
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}
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void usb_clock_reset(enum clk_usb clk_type, bool assert)
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{
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clock_reset(usb_cbcr[clk_type], assert);
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clock_reset(usb_mp_cbcr[clk_type], assert);
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}
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enum cb_err usb_prim_clock_enable(enum clk_usb_prim clk_type)
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{
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if (clk_type >= USB_PRIM_CLK_COUNT) {
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printk(BIOS_ERR, "USB C0 clock enable failed: "
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"clock type %d out of range\n", clk_type);
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return CB_ERR;
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}
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return clock_enable(usb_prim_cbcr[clk_type]);
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}
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void usb_prim_clock_reset(enum clk_usb_prim clk_type, bool assert)
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{
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clock_reset(usb_prim_cbcr[clk_type], assert);
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}
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enum cb_err usb_sec_clock_enable(enum clk_usb_sec clk_type)
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{
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if (clk_type >= USB_SEC_CLK_COUNT) {
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printk(BIOS_ERR, "USB C1 clock enable failed: "
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"clock type %d out of range\n", clk_type);
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return CB_ERR;
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}
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return clock_enable(usb_sec_cbcr[clk_type]);
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}
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void usb_sec_clock_reset(enum clk_usb_sec clk_type, bool assert)
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{
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clock_reset(usb_sec_cbcr[clk_type], assert);
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}
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void clock_configure_usb(void)
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{
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clock_configure(&gcc->usb30_mp_master_rcg,
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usb_core_cfg, USB3_MASTER_CLK_MIN_FREQ_HZ, ARRAY_SIZE(usb_core_cfg));
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clock_configure(&gcc->usb30_prim_master_rcg,
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usb_core_cfg, USB3_MASTER_CLK_MIN_FREQ_HZ, ARRAY_SIZE(usb_core_cfg));
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clock_configure(&gcc->usb30_sec_master_rcg,
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usb_core_cfg, USB3_MASTER_CLK_MIN_FREQ_HZ, ARRAY_SIZE(usb_core_cfg));
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}
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enum cb_err usb_clock_configure_mux(enum clk_pipe_usb clk_type, u32 src_type)
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@ -408,6 +479,13 @@ enum cb_err usb_clock_configure_mux(enum clk_pipe_usb clk_type, u32 src_type)
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case USB3_PHY_PIPE_1:
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write32(&gcc->gcc_usb3_mp_phy_pipe_1_muxr, src_type);
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break;
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case USB3_PRIM_PHY_PIPE:
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write32(&gcc->gcc_usb3_prim_phy_pipe_muxr, src_type);
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break;
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case USB3_SEC_PHY_PIPE:
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write32(&gcc->gcc_usb3_sec_phy_pipe_muxr, src_type);
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break;
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default:
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printk(BIOS_ERR, "Unhandled clk_type: %d, src_type: %u\n", clk_type, src_type);
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return CB_ERR;
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@ -70,6 +70,10 @@
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#define QUP_2_GSI_BASE 0x00804000
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/* USB BASE ADDRESSES */
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#define HS_USB_SS0_PHY_BASE 0x00FD3000
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#define HS_USB_SS1_PHY_BASE 0x00FD9000
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#define HS_USB_SS2_PHY_BASE 0x00FDE000
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#define HS_USB_MP0_PHY_BASE 0x088e1000
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#define HS_USB_MP1_PHY_BASE 0x088E2000
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#define QMP_PHY_MP0_QSERDES_COM_REG_BASE 0x088E3000
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@ -85,6 +89,26 @@
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#define QMP_PHY_MP1_PCS_REG_BASE 0x088E5200
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#define QMP_PHY_MP1_PCS_USB3_REG_BASE 0x088E6200
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/* USB SS0 PHY BASE ADDRESSES - AHB2PHY_1_QUSB4PHY_SS_0 */
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#define QMP_PHY_SS0_COM_REG_BASE 0xFD5000 // USB43DP_COM
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#define QMP_PHY_SS0_TXA_REG_BASE 0xFD5400 // USB43DP_QSERDES_TXA
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#define QMP_PHY_SS0_TXB_REG_BASE 0xFD5A00 // USB43DP_QSERDES_TXB
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#define QMP_PHY_SS0_RXA_REG_BASE 0xFD5600 // USB43DP_QSERDES_RXA
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#define QMP_PHY_SS0_RXB_REG_BASE 0xFD5C00 // USB43DP_QSERDES_RXB
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#define QMP_PHY_SS0_QSERDES_PLL_REG_BASE 0x00FD6000 // USB3_QSERDES_PLL
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#define QMP_PHY_SS0_PCS_REG_BASE 0xFD6400 // USB3_PCS
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#define QMP_PHY_SS0_PCS_USB3_REG_BASE 0xFD6700 // USB3_PCS_USB3
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/* USB SS1 PHY BASE ADDRESSES - AHB2PHY_1_QUSB4PHY_SS_1 */
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#define QMP_PHY_SS1_COM_REG_BASE 0xFDA000 // USB43DP_COM
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#define QMP_PHY_SS1_TXA_REG_BASE 0xFDA400 // USB43DP_QSERDES_TXA
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#define QMP_PHY_SS1_TXB_REG_BASE 0xFDAA00 // USB43DP_QSERDES_TXB
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#define QMP_PHY_SS1_RXA_REG_BASE 0xFDA600 // USB43DP_QSERDES_RXA
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#define QMP_PHY_SS1_RXB_REG_BASE 0xFDAC00 // USB43DP_QSERDES_RXB
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#define QMP_PHY_SS1_QSERDES_PLL_REG_BASE 0xFDB000 // USB3_QSERDES_PLL
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#define QMP_PHY_SS1_PCS_REG_BASE 0xFDB400 // USB3_PCS
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#define QMP_PHY_SS1_PCS_USB3_REG_BASE 0xFDB700 // USB3_PCS_USB3
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/* PCIE 6A */
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#define PCIE6A_PCIE_PARF 0x01BF8000
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#define PCIE6A_GEN1X4_PCIE_DBI 0x70000000
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@ -141,6 +165,8 @@
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#define TCSR_GCC_USB3_MP0_CLKREF_EN_ADDR ((void *)0x1FD510C)
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#define TCSR_GCC_USB3_MP1_CLKREF_EN_ADDR ((void *)0x1FD5110)
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#define TCSR_GCC_USB4_1_CLKREF_EN_ADDR ((void *)0x1FD5120)
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#define TCSR_GCC_USB4_2_CLKREF_EN_ADDR ((void *)0x1FD5124)
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#define USB3_CLKREF_ENABLE_VALUE 0x1
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/* SPMI PMIC ARB */
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@ -217,7 +217,10 @@ struct x1p42100_gcc {
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struct x1p42100_gpll gpll0;
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u8 _res0[0x10004 - 0x0002c];
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struct x1p42100_pcie_noc pcie_noc;
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u8 _res1[0x1200C - 0x10054];
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u8 _res1[0x12000 - 0x10054];
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u32 gcc_qusb2phy_prim_bcr;
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u32 gcc_qusb2phy_sec_bcr;
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u32 gcc_qusb2phy_tert_bcr;
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u32 qusb2phy_hs0_mp_bcr;
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u32 qusb2phy_hs1_mp_bcr;
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u8 _res2[0x17000 - 0x12014];
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@ -225,7 +228,7 @@ struct x1p42100_gcc {
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u32 gcc_usb30_mp_gdscr;
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u8 _res3[0x17018 - 0x17008];
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u32 gcc_usb30_mp_master_cbcr;
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u8 _res4[0x17024 - 0x1701C];
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u8 _res4[0x17024 - 0x1701c];
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u32 gcc_usb30_mp_sleep_cbcr;
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u32 gcc_usb30_mp_mock_utmi_cbcr;
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struct clock_rcg usb30_mp_master_rcg;
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@ -236,10 +239,10 @@ struct x1p42100_gcc {
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u32 gcc_usb3_mp_phy_pipe_0_muxr;
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u32 gcc_usb3_mp_phy_pipe_1_cbcr;
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u32 gcc_usb3_mp_phy_pipe_1_muxr;
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u8 _res6[0x173CC - 0x172A0];
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u8 _res6[0x173cc - 0x172a0];
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u32 gcc_cfg_noc_usb3_mp_axi_cbcr;
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u32 gcc_aggre_usb3_mp_axi_cbcr;
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u8 _res7[0x18004 - 0x173D4];
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u8 _res7[0x18004 - 0x173d4];
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struct qupv3_clock qup_wrap1_s[8];
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u8 _res8[0x19000 - 0x189c4];
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u32 usb3_uniphy_mp0_bcr;
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@ -275,59 +278,148 @@ struct x1p42100_gcc {
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u32 qup_wrap2_core_2x_cbcr;
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u8 _res19[0x232c4 - 0x232bc];
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struct clock_rcg qup_wrap2_core_2x;
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u8 _res20[0x2D014 - 0x232cc];
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u8 _res20[0x2a000 - 0x232cc];
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u32 gcc_usb3_phy_sec_bcr;
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u32 gcc_usb3phy_phy_sec_bcr;
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u8 _res21[0x2a010 - 0x2a008];
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u32 gcc_usb4_1_dp0_phy_sec_bcr;
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u8 _res22[0x2d014 - 0x2a014];
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u32 gcc_sys_noc_usb_axi_cbcr;
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u8 _res21[0x2D028 - 0x2D018];
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u8 _res23[0x2d024 - 0x2d018];
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u32 gcc_cfg_noc_usb_anoc_ahb_cbcr;
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u32 gcc_cfg_noc_usb_anoc_north_ahb_cbcr;
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u32 gcc_cfg_noc_usb_anoc_south_ahb_cbcr;
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u8 _res22[0x2D034 - 0x2D030];
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u8 _res24[0x2d034 - 0x2d030];
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u32 gcc_aggre_usb_noc_axi_cbcr;
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u8 _res23[0x2D174 - 0x2D038];
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u8 _res25[0x2d174 - 0x2d038];
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u32 gcc_aggre_noc_usb_south_axi_cbcr;
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u8 _res24[0x2D17C - 0x2D178];
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u8 _res26[0x2d17c - 0x2d178];
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u32 gcc_aggre_noc_usb_north_axi_cbcr;
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u8 _res25[0x31000 - 0x2D180];
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u8 _res27[0x31000 - 0x2d180];
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struct x1p42100_pcie pcie_6a;
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u8 res26[0x39000-0x3108c];
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u32 usb30_prim_bcr;
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u8 res27[0x42004-0x39004];
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u8 _res28[0x39000 - 0x3108c];
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u32 gcc_usb30_prim_bcr;
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u32 gcc_usb30_prim_gdscr;
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u8 _res29[0x39018 - 0x39008];
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u32 gcc_usb30_prim_master_cbcr;
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u8 _res30[0x39024 - 0x3901c];
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u32 gcc_usb30_prim_sleep_cbcr;
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u32 gcc_usb30_prim_mock_utmi_cbcr;
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struct clock_rcg usb30_prim_master_rcg;
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u8 _res31[0x39060 - 0x39034];
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u32 gcc_usb3_prim_phy_aux_cbcr;
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u32 gcc_usb3_prim_phy_com_aux_cbcr;
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u32 gcc_usb3_prim_phy_pipe_cbcr;
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u32 gcc_usb3_prim_phy_pipe_muxr;
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u32 gcc_usb4_mode_prim_phy_pipe_muxr;
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u8 _res32[0x3908c - 0x39074];
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u32 gcc_cfg_noc_usb3_prim_axi_cbcr;
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u32 gcc_aggre_usb3_prim_axi_cbcr;
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u8 _res33[0x42004 - 0x39094];
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struct qupv3_clock qup_wrap0_s[8];
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u8 _res28[0x4b000 - 0x429c4];
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u8 _res34[0x4b000 - 0x429c4];
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u32 qspi_bcr;
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u32 qspi_cnoc_ahb_cbcr;
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u32 qspi_core_cbcr;
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struct clock_rcg qspi_core;
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u8 _res29[0x52000 - 0x4b014];
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||||
u8 _res35[0x50000 - 0x4b014];
|
||||
u32 gcc_usb3_phy_prim_bcr;
|
||||
u32 gcc_usb3phy_phy_prim_bcr;
|
||||
u8 _res36[0x50010 - 0x50008];
|
||||
u32 gcc_usb4_0_dp0_phy_prim_bcr;
|
||||
u8 _res37[0x52000 - 0x50014];
|
||||
u32 apcs_clk_br_en;
|
||||
u8 _res30[0x52008 - 0x52004];
|
||||
u8 _res38[0x52008 - 0x52004];
|
||||
u32 apcs_clk_br_en1;
|
||||
u8 _res31[0x52010 - 0x5200c];
|
||||
u8 _res39[0x52010 - 0x5200c];
|
||||
u32 apcs_clk_br_en2;
|
||||
u8 _res32[0x52018 - 0x52014];
|
||||
u8 _res40[0x52018 - 0x52014];
|
||||
u32 apcs_clk_br_en3;
|
||||
u8 _res33[0x52020 - 0x5201c];
|
||||
u8 _res41[0x52020 - 0x5201c];
|
||||
u32 apcs_clk_br_en4;
|
||||
u8 _res34[0x52028 - 0x52024];
|
||||
u8 _res42[0x52028 - 0x52024];
|
||||
u32 apcs_clk_br_en5;
|
||||
u8 _res35[0x52030 - 0x5202c];
|
||||
u8 _res43[0x52030 - 0x5202c];
|
||||
u32 apcs_pll_br_en;
|
||||
u8 _res36[0x54000 - 0x52034];
|
||||
u8 _res44[0x54000 - 0x52034];
|
||||
u32 usb3_uniphy_mp1_bcr;
|
||||
u32 usb3uniphy_phy_mp1_bcr;
|
||||
u32 gcc_usb3_mp_ss1_phy_bcr;
|
||||
u32 gcc_usb3_mp_ss1_phy_gdscr;
|
||||
u8 _res37[0x8e000 - 0x54010];
|
||||
u8 _res45[0x8e000 - 0x54010];
|
||||
u32 pcie_6_phy_gdscr;
|
||||
u8 _res38[0xac01c - 0x8e004];
|
||||
u8 _res46[0xa1000 - 0x8e004];
|
||||
u32 gcc_usb30_sec_bcr;
|
||||
u32 gcc_usb30_sec_gdscr;
|
||||
u8 _res47[0xa1018 - 0xa1008];
|
||||
u32 gcc_usb30_sec_master_cbcr;
|
||||
u8 _res48[0xa1024 - 0xa101c];
|
||||
u32 gcc_usb30_sec_sleep_cbcr;
|
||||
u32 gcc_usb30_sec_mock_utmi_cbcr;
|
||||
struct clock_rcg usb30_sec_master_rcg;
|
||||
u8 _res49[0xa1060 - 0xa1034];
|
||||
u32 gcc_usb3_sec_phy_aux_cbcr;
|
||||
u32 gcc_usb3_sec_phy_com_aux_cbcr;
|
||||
u32 gcc_usb3_sec_phy_pipe_cbcr;
|
||||
u32 gcc_usb3_sec_phy_pipe_muxr;
|
||||
u8 _res50[0xa108c - 0xa1070];
|
||||
u32 gcc_cfg_noc_usb3_sec_axi_cbcr;
|
||||
u32 gcc_aggre_usb3_sec_axi_cbcr;
|
||||
u8 _res51[0xa2000 - 0xa1094];
|
||||
u32 gcc_usb30_tert_bcr;
|
||||
u32 gcc_usb30_tert_gdscr;
|
||||
u8 _res52[0xa2018 - 0xa2008];
|
||||
u32 gcc_usb30_tert_master_cbcr;
|
||||
u8 _res53[0xa2024 - 0xa201c];
|
||||
u32 gcc_usb30_tert_sleep_cbcr;
|
||||
u32 gcc_usb30_tert_mock_utmi_cbcr;
|
||||
u8 _res54[0xa2034 - 0xa202c];
|
||||
u32 gcc_usb30_tert_master_m;
|
||||
u32 gcc_usb30_tert_master_n;
|
||||
u32 gcc_usb30_tert_master_d;
|
||||
u8 _res55[0xa2060 - 0xa2040];
|
||||
u32 gcc_usb3_tert_phy_aux_cbcr;
|
||||
u32 gcc_usb3_tert_phy_com_aux_cbcr;
|
||||
u32 gcc_usb3_tert_phy_pipe_cbcr;
|
||||
u32 gcc_usb3_tert_phy_pipe_muxr;
|
||||
u8 _res56[0xa208c - 0xa2070];
|
||||
u32 gcc_cfg_noc_usb3_tert_axi_cbcr;
|
||||
u32 gcc_aggre_usb3_tert_axi_cbcr;
|
||||
u8 _res57[0xa3000 - 0xa2094];
|
||||
u32 gcc_usb3_phy_tert_bcr;
|
||||
u32 gcc_usb3phy_phy_tert_bcr;
|
||||
u8 _res58[0xa3010 - 0xa3008];
|
||||
u32 gcc_usb4_2_dp0_phy_tert_bcr;
|
||||
u8 _res59[0xac01c - 0xa3014];
|
||||
u32 pcie_6a_phy_bcr;
|
||||
};
|
||||
|
||||
check_member(x1p42100_gcc, gcc_usb30_prim_bcr, 0x39000);
|
||||
check_member(x1p42100_gcc, gcc_usb30_prim_master_cbcr, 0x39018);
|
||||
check_member(x1p42100_gcc, gcc_cfg_noc_usb3_prim_axi_cbcr, 0x3908c);
|
||||
check_member(x1p42100_gcc, gcc_usb30_sec_bcr, 0xa1000);
|
||||
check_member(x1p42100_gcc, gcc_usb30_sec_master_cbcr, 0xa1018);
|
||||
check_member(x1p42100_gcc, gcc_usb3_sec_phy_aux_cbcr, 0xa1060);
|
||||
check_member(x1p42100_gcc, gcc_usb30_tert_bcr, 0xa2000);
|
||||
check_member(x1p42100_gcc, gcc_qusb2phy_prim_bcr, 0x12000);
|
||||
check_member(x1p42100_gcc, gcc_qusb2phy_sec_bcr, 0x12004);
|
||||
check_member(x1p42100_gcc, gcc_qusb2phy_tert_bcr, 0x12008);
|
||||
check_member(x1p42100_gcc, qusb2phy_hs1_mp_bcr, 0x12010);
|
||||
check_member(x1p42100_gcc, gcc_usb3_phy_sec_bcr, 0x2a000);
|
||||
check_member(x1p42100_gcc, gcc_usb3phy_phy_sec_bcr, 0x2a004);
|
||||
check_member(x1p42100_gcc, gcc_usb4_1_dp0_phy_sec_bcr, 0x2a010);
|
||||
check_member(x1p42100_gcc, gcc_usb3_phy_prim_bcr, 0x50000);
|
||||
check_member(x1p42100_gcc, gcc_usb3phy_phy_prim_bcr, 0x50004);
|
||||
check_member(x1p42100_gcc, gcc_usb4_0_dp0_phy_prim_bcr, 0x50010);
|
||||
check_member(x1p42100_gcc, gcc_usb3_phy_tert_bcr, 0xa3000);
|
||||
check_member(x1p42100_gcc, gcc_usb3phy_phy_tert_bcr, 0xa3004);
|
||||
check_member(x1p42100_gcc, gcc_usb4_2_dp0_phy_tert_bcr, 0xa3010);
|
||||
check_member(x1p42100_gcc, gcc_usb30_mp_bcr, 0x17000);
|
||||
check_member(x1p42100_gcc, qup_wrap1_s, 0x18004);
|
||||
check_member(x1p42100_gcc, gcc_usb30_mp_master_cbcr, 0x17018);
|
||||
check_member(x1p42100_gcc, gcc_usb30_mp_sleep_cbcr, 0x17024);
|
||||
check_member(x1p42100_gcc, gcc_usb3_mp_phy_aux_cbcr, 0x17288);
|
||||
check_member(x1p42100_gcc, gcc_cfg_noc_usb3_mp_axi_cbcr, 0x173CC);
|
||||
check_member(x1p42100_gcc, gcc_cfg_noc_usb3_mp_axi_cbcr, 0x173cc);
|
||||
check_member(x1p42100_gcc, qup_wrap2_s, 0x1e004);
|
||||
check_member(x1p42100_gcc, qup_wrap0_m_ahb_cbcr, 0x23000);
|
||||
check_member(x1p42100_gcc, qup_wrap0_core_cdivr, 0x23014);
|
||||
|
|
@ -338,11 +430,11 @@ check_member(x1p42100_gcc, qup_wrap1_core_2x, 0x23174);
|
|||
check_member(x1p42100_gcc, qup_wrap2_m_ahb_cbcr, 0x232a0);
|
||||
check_member(x1p42100_gcc, qup_wrap2_core_cdivr, 0x232b4);
|
||||
check_member(x1p42100_gcc, qup_wrap2_core_2x, 0x232c4);
|
||||
check_member(x1p42100_gcc, gcc_sys_noc_usb_axi_cbcr, 0x2D014);
|
||||
check_member(x1p42100_gcc, gcc_cfg_noc_usb_anoc_north_ahb_cbcr, 0x2D028);
|
||||
check_member(x1p42100_gcc, gcc_aggre_usb_noc_axi_cbcr, 0x2D034);
|
||||
check_member(x1p42100_gcc, gcc_aggre_noc_usb_south_axi_cbcr, 0x2D174);
|
||||
check_member(x1p42100_gcc, gcc_aggre_noc_usb_north_axi_cbcr, 0x2D17C);
|
||||
check_member(x1p42100_gcc, gcc_sys_noc_usb_axi_cbcr, 0x2d014);
|
||||
check_member(x1p42100_gcc, gcc_cfg_noc_usb_anoc_north_ahb_cbcr, 0x2d028);
|
||||
check_member(x1p42100_gcc, gcc_aggre_usb_noc_axi_cbcr, 0x2d034);
|
||||
check_member(x1p42100_gcc, gcc_aggre_noc_usb_south_axi_cbcr, 0x2d174);
|
||||
check_member(x1p42100_gcc, gcc_aggre_noc_usb_north_axi_cbcr, 0x2d17c);
|
||||
check_member(x1p42100_gcc, qup_wrap0_s, 0x42004);
|
||||
check_member(x1p42100_gcc, qspi_bcr, 0x4b000);
|
||||
check_member(x1p42100_gcc, apcs_clk_br_en, 0x52000);
|
||||
|
|
@ -437,6 +529,8 @@ enum clk_usb_gdsc {
|
|||
USB30_MP_GDSC,
|
||||
USB3_SS0_PHY_GDSC,
|
||||
USB3_SS1_PHY_GDSC,
|
||||
USB30_PRIM_GDSC,
|
||||
USB30_SEC_GDSC,
|
||||
MAX_USB_GDSC,
|
||||
};
|
||||
enum clk_usb {
|
||||
|
|
@ -458,9 +552,46 @@ enum clk_usb {
|
|||
USB_CLK_COUNT,
|
||||
};
|
||||
|
||||
enum clk_usb_prim {
|
||||
USB_PRIM_SYS_NOC_USB_AXI_CBCR,
|
||||
USB_PRIM_CFG_NOC_USB_ANOC_AHB_CBCR,
|
||||
USB_PRIM_CFG_NOC_USB_ANOC_NORTH_AHB_CBCR,
|
||||
USB_PRIM_CFG_NOC_USB_ANOC_SOUTH_AHB_CBCR,
|
||||
USB_PRIM_AGGRE_USB_NOC_AXI_CBCR,
|
||||
USB_PRIM_AGGRE_NOC_USB_SOUTH_AXI_CBCR,
|
||||
USB_PRIM_AGGRE_NOC_USB_NORTH_AXI_CBCR,
|
||||
USB_PRIM_USB30_PRIM_MASTER_CBCR,
|
||||
USB_PRIM_USB30_PRIM_SLEEP_CBCR,
|
||||
USB_PRIM_USB30_PRIM_MOCK_UTMI_CBCR,
|
||||
USB_PRIM_USB3_PRIM_PHY_AUX_CBCR,
|
||||
USB_PRIM_USB3_PRIM_PHY_COM_AUX_CBCR,
|
||||
USB_PRIM_USB3_PRIM_PHY_PIPE_CBCR,
|
||||
USB_PRIM_CFG_NOC_USB3_PRIM_AXI_CBCR,
|
||||
USB_PRIM_AGGRE_USB3_PRIM_AXI_CBCR,
|
||||
USB_PRIM_CLK_COUNT,
|
||||
};
|
||||
|
||||
enum clk_usb_sec {
|
||||
USB_SEC_CFG_NOC_USB3_SEC_AXI_CBCR,
|
||||
USB_SEC_AGGRE_USB3_SEC_AXI_CBCR,
|
||||
USB_SEC_USB30_SEC_MASTER_CBCR,
|
||||
USB_SEC_USB30_SEC_SLEEP_CBCR,
|
||||
USB_SEC_USB30_SEC_MOCK_UTMI_CBCR,
|
||||
USB_SEC_USB3_SEC_PHY_AUX_CBCR,
|
||||
USB_SEC_USB3_SEC_PHY_COM_AUX_CBCR,
|
||||
USB_SEC_USB3_SEC_PHY_PIPE_CBCR,
|
||||
USB_SEC_AGGRE_USB_NOC_AXI_CBCR,
|
||||
USB_SEC_AGGRE_NOC_USB_NORTH_AXI_CBCR,
|
||||
USB_SEC_AGGRE_NOC_USB_SOUTH_AXI_CBCR,
|
||||
USB_SEC_SYS_NOC_USB_AXI_CBCR,
|
||||
USB_SEC_CLK_COUNT,
|
||||
};
|
||||
|
||||
enum clk_pipe_usb {
|
||||
USB3_PHY_PIPE_0,
|
||||
USB3_PHY_PIPE_1,
|
||||
USB3_PRIM_PHY_PIPE,
|
||||
USB3_SEC_PHY_PIPE,
|
||||
USB3_PIPE_CLK_COUNT
|
||||
};
|
||||
|
||||
|
|
@ -486,7 +617,13 @@ enum cb_err clock_configure_mux(enum clk_pcie clk_type, u32 src_type);
|
|||
enum cb_err usb_clock_configure_mux(enum clk_pipe_usb clk_type, u32 src_type);
|
||||
enum cb_err usb_clock_enable(enum clk_usb clk_type);
|
||||
enum cb_err clock_enable_usb_gdsc(enum clk_usb_gdsc gdsc_type);
|
||||
enum cb_err usb_prim_clock_enable(enum clk_usb_prim clk_type);
|
||||
enum cb_err usb_sec_clock_enable(enum clk_usb_sec clk_type);
|
||||
|
||||
void usb_clock_reset(enum clk_usb clk_type, bool assert);
|
||||
void usb_prim_clock_reset(enum clk_usb_prim clk_type, bool assert);
|
||||
void usb_sec_clock_reset(enum clk_usb_sec clk_type, bool assert);
|
||||
|
||||
/* Subsystem Reset */
|
||||
static struct aoss *const aoss = (void *)AOSS_CC_BASE;
|
||||
static struct x1p42100_gcc *const gcc = (void *)GCC_BASE;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue